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MIAOW (pronounced "me-ow") [Many-core Integrated Accelerator Of Waterdeep/Wisconsin] is an open source GPU created by the Vertical Research Group at the University of Wisconsin-Madison led by Professor Karu Sankaralingam. Based off of the publicly released Southern Islands ISA by AMD, MIAOW implements a compute unit suitable for performing architecture analysis and experimentation with GPGPU workloads. In addition to the Verilog HDL composing the compute unit, MIAOW also includes a suite of unit tests and benchmarks for regression testing.
A primary motivator for MIAOW's creation is the belief that software simulators of hardware such as CPUs and GPUs often miss many subtle aspects that can skew the performance, power, and other quantitative results that they produce. As an actual implementation of a GPU's logic, the Vertical Research Group believes that MIAOW can be a useful tool in producing not only more accurate quantitative results when benchmarking GPGPU workloads but also provide context for the architectural complexities of actually implementing newly proposed algorithms and designs that are intended to improve performance or other desired characteristics.
It must be emphasized that MIAOW represents a GPU's compute unit. It does not possess the auxiliary logic required to produce actual graphical output nor does it have logic to connect it to a specific memory interface or system bus. These extensions can be developed and we would welcome outside contributors for such efforts, but as MIAOW was created as a research tool their presence was not an absolute necessity in running benchmarks and experiments.
MIAOW is licensed under the 3-clause BSD license.
MIAOW is being released in phases as we complete the necessary preparation and packaging. Be sure to check this section to see what has been made available and what we hope to make available in the near future.
- RTL implementation of MIAOW compute unit
- Testbench for verification
- Benchmarks (instruction and data traces) that are known to run on MIAOW (derived from AMD APP SDK)
- FPGA bootstrapping framework
- Synthesis scripts for area and power analysis
- Verilog for hardware dispatcher for controlling multiple CUs
- Patch for multi2sim simulator to generate reference instruction traces
- Case Studies Documentation
- Workload development
MIAOW can be used under a variety of situations, some straightforward and others not so. Documentation is split across both this wiki as well as third party links where relevant.
- Architecture - Detailed description of the internal design of each module. This information is useful for understanding how modifications to MIAOW affects the entire pipeline.
The below documentation is organized based on complexity of the use case.
- Bringup and Verification - Setup of a MIAOW build and running of tests to verify that synthesis was successful.
- Extension and Verification - Extending MIAOW to support additional instructions and how to generate unit tests for the new functionality.
- Micro-architectural Extension and Verification - Examples of how to make changes to MIAOW's micro-architecture in the form of case studies. TODO
- Neko - FPGA bringup of MIAOW.
The Vertical Research Group welcomes anyone who wishes to contribute to MIAOW's development. As previously noted MIAOW is primarily an implementation of a GPU's compute unit. To produce a functional graphics card would require several peripheral modules that interface with the host system, memory, and of course provide video output. The subset of the Southern Islands ISA MIAOW supports would also need to be expanded to also include instructions related to graphics operations. Another substantial component would be a module to handle texture operations, which requires some specialized logic relative to the rest of the GPU.
As MIAOW is hosted on github, we intend to make use of github's facilities for reviewing and accepting contributions. We will not ask for copyright assignment of contributions, simply that any contributions be made available under the 3-clause BSD license.
You can contact us via the email [email protected] or participate in group discussions at [email protected].
- Raghuraman Balasubramanian
- Vinay Gangadhar
- Mario Paulo Drumond
- Ziliang Guo
- Chen-Han Ho
- Cherin Joseph
- Jaikrishnan Menon
- Robin Paul
- Sharath Prasad
- Pradip Vallathol
We would also like to thank Professor Sankaralingam for shepherding this project and showing the patience to see it to fruition.