Skip to content

Update project tt_um_aidenfoxivey (aidenfoxivey/tt07-verilog-template) #23

Update project tt_um_aidenfoxivey (aidenfoxivey/tt07-verilog-template)

Update project tt_um_aidenfoxivey (aidenfoxivey/tt07-verilog-template) #23

Triggered via pull request May 9, 2024 02:29
Status Success
Total duration 2m 34s
Artifacts 2

project_submission.yaml

on: pull_request
Check user project submission
42s
Check user project submission
Run precheck
2m 26s
Run precheck
Fit to window
Zoom out
Zoom in

Artifacts

Produced during runtime
Name Size
precheck-reports Expired
5.93 KB
shuttle_index Expired
1.24 KB