Update project tt_um_aidenfoxivey (aidenfoxivey/tt07-verilog-template) #23
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…g-template Commit: ad99cd0eea15a6364ec62136f5d11c1434b5e5a8 Workflow: https://github.com/aidenfoxivey/tt07-verilog-template/actions/runs/9011435901
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Update project tt_um_aidenfoxivey to commit aidenfoxivey/tt07-verilog-template@ad99cd0eea15a6364ec62136f5d11c1434b5e5a8
Project title: CRC-8 CCITT
Tiles: 1x1
Workflow: https://github.com/aidenfoxivey/tt07-verilog-template/actions/runs/9011435901