Can not synthesize verilog code as the reference

[young03600]

Description

I'm running deisgn genericfir using openlane
I've tried some arguments listed in the Flow Configuration Variables but the synthesized netlist seems weird compared with a synthesized reference.

The genericfir design only maps to sky130_fd_sc_hd__conb_1 cells.
It seems that we do not have the tapk module so that's the reason why I guess?
If it's not solvable, is there any way to reuse the synthesize one to do the PnR flow just skip the synthesis stage?

Thanks in advance.

Expected Behavior

The files are the reference and the problem one genericfir.zip

Environment report

Failed to get distribution info.
Kernel: Linux v5.15.0-127-generic
Python: v3.11.9 (OK)
Critical Alert: No Docker or Docker-compatible container engine was found.
OpenLane Git Version: 3876562d27af3f6825a823941b1cab36f7eb6dc3
python-venv: INSTALLED
---
PDK Version Verification Status: OK
---
Git Log (Last 3 Commits)

3876562 2024-10-05T02:47:02+03:00 hotfix: main branch hashes not being pushed to dockerhub - Mohamed Gaber -  (grafted, HEAD -> master, tag: 1.1.1, origin/master, origin/HEAD)
---
Git Remotes

origin  https://github.com/The-OpenROAD-Project/OpenLane.git (fetch)
origin  https://github.com/The-OpenROAD-Project/OpenLane.git (push)

Reproduction material

As the designs are opencores so the verilog code can be found on the github, I used the one: genericfir.v
The config used in genericfir/config.json

{
    "DESIGN_NAME": "genericfir",
    "VERILOG_FILES": "dir::src/*.v",
    "CLOCK_PORT": "i_clk",
    "CLOCK_NET": "i_clk",
    "CLOCK_PERIOD": 10.0,
    "FP_PDN_MULTILAYER": true,
    "RUN_LINTER": 0,
    "QUIT_ON_SYNTH_CHECKS": 0,
    "pdk::sky130A": {
        "MAX_FANOUT_CONSTRAINT": 7,
        "FP_CORE_UTIL": 10,
        "GLB_RT_ADJUSTMENT": 0.1,
        "PL_TARGET_DENSITY": "expr::($FP_CORE_UTIL + 5.0) / 100.0",
        "ROUTING_CORES": 6,
        "scl::sky130_fd_sc_hd": {
            "CLOCK_PERIOD": 10,
            "SYNTH_STRATEGY": "DELAY 2",
            "SYNTH_TIMING_DERATE": "0",
            "SYNTH_DRIVING_CELL": "sky130_fd_sc_hd__inv_8",
            "SYNTH_CLOCK_TRANSITION": 0,
            "SYNTH_CLOCK_UNCERTAINTY": 0
        }
    }
}

Relevant log output

63. Printing statistics.

=== genericfir ===

   Number of wires:                  7
   Number of wire bits:             59
   Number of public wires:           7
   Number of public wire bits:      59
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 31
     sky130_fd_sc_hd__conb_1        31

   Chip area for module '\genericfir': 116.361600

64. Executing Verilog backend.
Dumping module `\genericfir'.

65. Executing JSON backend.

Warnings: 18 unique messages, 18 total
End of script. Logfile hash: 6c300f20c7, CPU: user 15.14s system 0.28s, MEM: 946.61 MB peak
Yosys 0.38 (git sha1 543faed9c8c, clang++ 17.0.6 -fPIC -Os)
Time spent: 33% 276x opt_clean (5 sec), 25% 277x opt_expr (3 sec), ...