Increase banner size for OpenLane 2 (#2137)

~ Increases banner size for OpenLane 2, now uses a PNG rendered at 1200 API on macOS for consistency ~ Updated Flow Architecture Document Co-authored-by: Mohamed Gaber <[email protected]>
The-OpenROAD-Project · Jul 18, 2024 · 7ee9285 · 7ee9285
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diff --git a/README.md b/README.md
@@ -1,6 +1,6 @@
 <p align="center">
     <a href="https://github.com/efabless/openlane2">
-        <img src="./docs/_static/ol2_banner.svg" alt="Banner explaining that OpenLane is currently only for hardening Caravel User Project-based designs targeting chipIgnite"/>
+        <img src="./docs/_static/ol2_banner.png" style="width: 70%;overflow: visible" alt="Banner explaining that OpenLane is currently only for hardening Caravel User Project-based designs targeting chipIgnite"/>
     </a>
 </p>
 

diff --git a/docs/_static/eco_flow.png b/docs/_static/eco_flow.png
diff --git a/docs/_static/eco_results.png b/docs/_static/eco_results.png
diff --git a/docs/_static/flow.png b/docs/_static/flow.png
diff --git a/docs/_static/flow_v1.png b/docs/_static/flow_v1.png
diff --git a/docs/_static/ol2_banner.png b/docs/_static/ol2_banner.png
diff --git a/docs/_static/ol2_banner.svg b/docs/_static/ol2_banner.svg
diff --git a/docs/_static/striVe.jpeg b/docs/_static/striVe.jpeg
diff --git a/docs/source/flow_overview.md b/docs/source/flow_overview.md
@@ -1,55 +1,44 @@
 # OpenLane Architecture
 
-![A diagram showing the general stages of the OpenLane flow as a series of blocks](../_static/flow_v1.png)
+![A diagram showing the general stages of the OpenLane flow as a series of blocks](../_static/flow.png)
 
-
-## OpenLane Design Stages
+## OpenLane Flow Stages
 
 OpenLane flow consists of several stages. By default all flow steps are run in sequence. Each stage may consist of multiple sub-stages. OpenLane can also be run interactively as shown [here][25].
 
 1. **Synthesis**
-    1. `yosys/abc` - Perform RTL synthesis and technology mapping.
-    2. `OpenSTA` - Performs static timing analysis on the resulting netlist to generate timing reports
+    1. [Yosys](https://github.com/yosyshq/yosys) - Perform RTL synthesis and technology mapping.
+    2. [OpenSTA](https://github.com/the-openroad-project/opensta) - Performs static timing analysis on the resulting netlist to generate timing reports
 2. **Floorplaning**
-    1. `init_fp` - Defines the core area for the macro as well as the rows (used for placement) and the tracks (used for routing)
-    2. `ioplacer` - Places the macro input and output ports
-    3. `pdngen` - Generates the power distribution network
-    4. `tapcell` - Inserts welltap and decap cells in the floorplan
+    1. [OpenROAD/Initialize Floorplan](https://github.com/the-openroad-project/openroad/tree/master/src/ifp) - Defines the core area for the macro as well as the rows (used for placement) and the tracks (used for routing)
+    2. OpenLane IO Placer - Places the macro input and output ports
+    3. [OpenROAD/PDN Generator](https://github.com/the-openroad-project/openroad/tree/master/src/pdn) - Generates the power distribution network
+    4. [OpenROAD/Tapcell](https://github.com/the-openroad-project/openroad/tree/master/src/tap)  - Inserts welltap and endcap cells in the floorplan
 3. **Placement**
-    1. `RePLace` - Performs global placement
-    2. `Resizer` - Performs optional optimizations on the design
-    3. `OpenDP` - Performs detailed placement to legalize the globally placed components
+    1. [OpenROAD/RePlace](https://github.com/the-openroad-project/openroad/tree/master/src/gpl) - Performs global placement
+    2. [OpenROAD/Resizer](https://github.com/the-openroad-project/openroad/tree/master/src/rsz)  - Performs optional optimizations on the design
+    3. [OpenROAD/OpenDP](https://github.com/the-openroad-project/openroad/tree/master/src/dpl)  - Performs detailed placement to legalize the globally placed components
 4. **CTS**
-    1. `TritonCTS` - Synthesizes the clock distribution network (the clock tree)
+    1. [OpenROAD/TritonCTS](https://github.com/the-openroad-project/openroad/tree/master/src/cts)  - Synthesizes the clock distribution network (the clock tree)
 5. **Routing**
-    1. `FastRoute` - Performs global routing to generate a guide file for the detailed router
-    2. `TritonRoute` - Performs detailed routing
-    3. `OpenRCX` - Performs SPEF extraction
+    1. [OpenROAD/FastRoute](https://github.com/the-openroad-project/openroad/tree/master/src/grt) - Performs global routing to generate a guide file for the detailed router
+    2. [OpenROAD/TritonRoute](https://github.com/the-openroad-project/openroad/tree/master/src/drt) - Performs detailed routing
+    3. [OpenROAD/OpenRCX](https://github.com/the-openroad-project/openroad/tree/master/src/rcx) - Performs SPEF extraction
 6. **Tapeout**
-    1. `Magic` - Streams out the final GDSII layout file from the routed def
-    2. `KLayout` - Streams out the final GDSII layout file from the routed def as a back-up
+    1. [Magic](https://github.com/rtimothyedwards/magic) - Streams out the final GDSII layout file from the routed def
+    2. [KLayout](https://github.com/klayout/klayout) - Streams out the final GDSII layout file from the routed def as a back-up
 7. **Signoff**
-    1. `Magic` - Performs DRC Checks & Antenna Checks
-    2. `KLayout` - Performs DRC Checks
-    3. `Netgen` - Performs LVS Checks
-    4. `CVC` - Performs Circuit Validity Checks
-
-OpenLane integrated several key open source tools over the execution stages:
-- RTL Synthesis, Technology Mapping, and Formal Verification : [yosys + abc][4]
-- Static Timing Analysis: [OpenSTA][8]
-- Floor Planning: [init_fp][5], [ioPlacer][6], [pdn][16] and [tapcell][7]
-- Placement: [RePLace][9] (Global), [Resizer][15] and [OpenPhySyn][28] (formerly), and [OpenDP][10] (Detailed)
-- Clock Tree Synthesis: [TritonCTS][11]
-- Fill Insertion: [OpenDP/filler_placement][10]
-- Routing: [FastRoute][12] or [CU-GR][36] (formerly) and [TritonRoute][13] (Detailed) or [DR-CU][36]
-- SPEF Extraction: [OpenRCX][37] or [SPEF-Extractor][27] (formerly)
-- GDSII Streaming out: [Magic][14] and [KLayout][35]
-- DRC Checks: [Magic][14] and [KLayout][35]
-- LVS check: [Netgen][22]
-- Antenna Checks: [Magic][14]
-- Circuit Validity Checker: [CVC][31]
-
-> Everything in Floorplanning through Routing is done using [OpenROAD](https://github.com/The-OpenROAD-Project/OpenROAD) and its various sub-utilities.
+    1. [Magic](https://github.com/rtimothyedwards/magic) - Performs DRC Checks & Antenna Checks
+    2. [Magic](https://github.com/klayout/klayout) - Performs DRC Checks & an XOR sanity-check between the two generated GDS-II files
+    3. [Netgen](https://github.com/rtimothyedwards/netgen) - Performs LVS Checks
+
+All tools in the OpenLane flow are free, libre and open-source software. While
+OpenLane itself as a script (and its associated build scripts) are under the
+Apache License, version 2.0, tools may fall under stricter licenses.
+
+> Everything in Floorplanning through Routing is done using
+> [OpenROAD](https://github.com/The-OpenROAD-Project/OpenROAD) and its various
+> sub-utilities, hence the name "OpenLane."
 
 ## OpenLane Output
 
@@ -79,40 +68,4 @@ All output run data is placed by default under ./designs/design_name/runs. Each
 ```
 
 To delete all generated runs under all designs:
-`make clean_runs`
-
-[1]: ../for_developers/docker.md
-[4]: https://github.com/YosysHQ/yosys
-[5]: https://github.com/The-OpenROAD-Project/OpenROAD/tree/master/src/ifp
-[6]: https://github.com/The-OpenROAD-Project/OpenROAD/tree/master/src/ppl
-[7]: https://github.com/The-OpenROAD-Project/OpenROAD/tree/master/src/tap
-[8]: https://github.com/The-OpenROAD-Project/OpenSTA
-[9]: https://github.com/The-OpenROAD-Project/OpenROAD/tree/master/src/replace
-[10]: https://github.com/The-OpenROAD-Project/OpenROAD/tree/master/src/dpl
-[11]: https://github.com/The-OpenROAD-Project/OpenROAD/tree/master/src/cts
-[12]: https://github.com/The-OpenROAD-Project/OpenROAD/tree/master/src/grt
-[13]: https://github.com/The-OpenROAD-Project/OpenROAD/tree/master/src/TritonRoute
-[14]: https://github.com/RTimothyEdwards/magic
-[15]: https://github.com/The-OpenROAD-Project/OpenROAD/tree/master/src/rsz
-[16]: https://github.com/The-OpenROAD-Project/OpenROAD/tree/master/src/pdn
-[18]: https://github.com/RTimothyEdwards/qflow/blob/master/src/addspacers.c
-[19]: https://github.com/The-OpenROAD-Project/
-[20]: https://github.com/git-lfs/git-lfs/wiki/Installation
-[21]: /usage/exploration_script.md
-[22]: https://github.com/RTimothyEdwards/netgen
-[24]: ./for_developers/pdk_structure.md
-[25]: ./reference/interactive_mode.md
-[26]: ./usage/chip_integration.md
-[27]: https://github.com/AUCOHL/spef-extractor
-[28]: https://github.com/scale-lab/OpenPhySyn
-[29]: ./usage/hardening_macros.md
-[30]: ./usage/building_the_pdk.md
-[31]: https://github.com/d-m-bailey/cvc
-[32]: ./for_developers/code_contribution.md
-[33]: ./authors.md
-[34]: ./reference/openlane_commands.md
-[35]: https://github.com/KLayout/klayout
-[36]: https://github.com/cuhk-eda/cu-gr
-[37]: https://github.com/The-OpenROAD-Project/OpenROAD/tree/master/src/rcx
-[38]: ./for_developers/issue_regression_tests.md
-[39]: https://github.com/cuhk-eda/dr-cu
+`make clean_runs`.