Merge branch 'develop'

.travis.yml

@@ -4,14 +4,16 @@ sudo: false
 
 python:
   - 3.7
+  - 3.8
+  - 3.9
 
 addons:
   apt:
     packages:
     - iverilog
 
 install:
-  - pip install pytest pytest-pythonpath jinja2
+  - pip install pytest pytest-pythonpath jinja2 ply
 
 script:
   - python -m pytest tests

README.md

@@ -13,8 +13,6 @@ License
 
 Apache License 2.0 (http://www.apache.org/licenses/LICENSE-2.0)
 
-Note that this software package includes PLY-3.4 in "vparser/ply". The license of PLY is BSD.
-
 
 Publication
 ==============================
@@ -65,7 +63,7 @@ for pull requests
 
 Please check "CONTRIBUTORS.md" for the contributors who provided pull requests.
 
-Pyverilog uses **pytest** for the integration testing. **When you send a pull request, please include a testing example with pytest.** 
+Pyverilog uses **pytest** for the integration testing. **When you send a pull request, please include a testing example with pytest.**
 To write a testing code, please refer the existing testing examples in "tests" directory.
 
 If the pull request code passes all the tests successfully and has no obvious problem, it will be merged to the *develop* branch by the main committers.
@@ -77,17 +75,18 @@ Installation
 Requirements
 --------------------
 
-- Python3: 3.6 or later
+- Python3: 3.7 or later
 - Icarus Verilog: 10.1 or later
 
 ```
 sudo apt install iverilog
 ```
 
 - Jinja2: 2.10 or later
+- PLY: 3.4 or later
 
 ```
-pip3 install jinja2
+pip3 install jinja2 ply
 ```
 
 Optional installation for testing

examples/example_active_analyzer.py

@@ -7,39 +7,41 @@
 # the next line can be removed after installation
 sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.abspath(__file__))))
 
-import pyverilog.utils.version
+import pyverilog
 import pyverilog.utils.util as util
 import pyverilog.controlflow.splitter as splitter
 from pyverilog.dataflow.dataflow_analyzer import VerilogDataflowAnalyzer
 from pyverilog.dataflow.optimizer import VerilogDataflowOptimizer
 from pyverilog.controlflow.active_analyzer import VerilogActiveConditionAnalyzer
 
+
 def main():
     INFO = "Active condition analyzer"
-    VERSION = pyverilog.utils.version.VERSION
+    VERSION = pyverilog.__version__
     USAGE = "Usage: python example_active_analyzer.py -t TOPMODULE file ..."
 
     def showVersion():
         print(INFO)
         print(VERSION)
         print(USAGE)
         sys.exit()
-    
+
     optparser = OptionParser()
-    optparser.add_option("-v","--version",action="store_true",dest="showversion",
-                         default=False,help="Show the version")
-    optparser.add_option("-t","--top",dest="topmodule",
-                         default="TOP",help="Top module, Default=TOP")
-    optparser.add_option("-s","--search",dest="searchtarget",action="append",
-                         default=[],help="Search Target Signal")
+    optparser.add_option("-v", "--version", action="store_true", dest="showversion",
+                         default=False, help="Show the version")
+    optparser.add_option("-t", "--top", dest="topmodule",
+                         default="TOP", help="Top module, Default=TOP")
+    optparser.add_option("-s", "--search", dest="searchtarget", action="append",
+                         default=[], help="Search Target Signal")
     (options, args) = optparser.parse_args()
 
     filelist = args
     if options.showversion:
         showVersion()
 
     for f in filelist:
-        if not os.path.exists(f): raise IOError("file not found: " + f)
+        if not os.path.exists(f):
+            raise IOError("file not found: " + f)
 
     if len(filelist) == 0:
         showVersion()
@@ -58,25 +60,28 @@ def showVersion():
     resolved_binddict = optimizer.getResolvedBinddict()
     constlist = optimizer.getConstlist()
 
-    canalyzer = VerilogActiveConditionAnalyzer(options.topmodule, terms, binddict, 
+    canalyzer = VerilogActiveConditionAnalyzer(options.topmodule, terms, binddict,
                                                resolved_terms, resolved_binddict, constlist)
 
     for target in options.searchtarget:
         signal = util.toTermname(target)
 
-        active_conditions = canalyzer.getActiveConditions( signal )
+        active_conditions = canalyzer.getActiveConditions(signal)
         #active_conditions = canalyzer.getActiveConditions( signal, condition=splitter.active_modify )
         #active_conditions = canalyzer.getActiveConditions( signal, condition=splitter.active_unmodify )
 
         print('Active Cases: %s' % signal)
-        for fsm_sig, active_conditions in sorted(active_conditions.items(), key=lambda x:str(x[0])):
+        for fsm_sig, active_conditions in sorted(active_conditions.items(), key=lambda x: str(x[0])):
             print('FSM: %s' % fsm_sig)
-            for state, active_condition in sorted(active_conditions, key=lambda x:str(x[0])):
+            for state, active_condition in sorted(active_conditions, key=lambda x: str(x[0])):
                 s = []
                 s.append('state: %d -> ' % state)
-                if active_condition: s.append(active_condition.tocode())
-                else: s.append('empty')
+                if active_condition:
+                    s.append(active_condition.tocode())
+                else:
+                    s.append('empty')
                 print(''.join(s))
 
+
 if __name__ == '__main__':
     main()

examples/example_active_range.py

@@ -7,38 +7,40 @@
 # the next line can be removed after installation
 sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.abspath(__file__))))
 
-import pyverilog.utils.version
+import pyverilog
 import pyverilog.utils.util as util
 from pyverilog.dataflow.dataflow_analyzer import VerilogDataflowAnalyzer
 from pyverilog.dataflow.optimizer import VerilogDataflowOptimizer
 from pyverilog.controlflow.active_range import VerilogActiveAnalyzer
 
+
 def main():
     INFO = "Active condition analyzer (Obsoluted)"
-    VERSION = pyverilog.utils.version.VERSION
+    VERSION = pyverilog.__version__
     USAGE = "Usage: python example_active_range.py -t TOPMODULE file ..."
 
     def showVersion():
         print(INFO)
         print(VERSION)
         print(USAGE)
         sys.exit()
-    
+
     optparser = OptionParser()
-    optparser.add_option("-v","--version",action="store_true",dest="showversion",
-                         default=False,help="Show the version")
-    optparser.add_option("-t","--top",dest="topmodule",
-                         default="TOP",help="Top module, Default=TOP")
-    optparser.add_option("-s","--search",dest="searchtarget",action="append",
-                         default=[],help="Search Target Signal")
+    optparser.add_option("-v", "--version", action="store_true", dest="showversion",
+                         default=False, help="Show the version")
+    optparser.add_option("-t", "--top", dest="topmodule",
+                         default="TOP", help="Top module, Default=TOP")
+    optparser.add_option("-s", "--search", dest="searchtarget", action="append",
+                         default=[], help="Search Target Signal")
     (options, args) = optparser.parse_args()
 
     filelist = args
     if options.showversion:
         showVersion()
 
     for f in filelist:
-        if not os.path.exists(f): raise IOError("file not found: " + f)
+        if not os.path.exists(f):
+            raise IOError("file not found: " + f)
 
     if len(filelist) == 0:
         showVersion()
@@ -57,27 +59,28 @@ def showVersion():
     resolved_binddict = optimizer.getResolvedBinddict()
     constlist = optimizer.getConstlist()
 
-    aanalyzer = VerilogActiveAnalyzer(options.topmodule, terms, binddict, 
+    aanalyzer = VerilogActiveAnalyzer(options.topmodule, terms, binddict,
                                       resolved_terms, resolved_binddict, constlist)
 
     for target in options.searchtarget:
         signal = util.toTermname(target)
 
         print('Active Conditions: %s' % signal)
-        active_conditions = aanalyzer.getActiveConditions( signal )
-        print(sorted(active_conditions, key=lambda x:str(x)))
+        active_conditions = aanalyzer.getActiveConditions(signal)
+        print(sorted(active_conditions, key=lambda x: str(x)))
 
         print('Changed Conditions')
-        changed_conditions = aanalyzer.getChangedConditions( signal )
-        print(sorted(changed_conditions, key=lambda x:str(x)))
-    
+        changed_conditions = aanalyzer.getChangedConditions(signal)
+        print(sorted(changed_conditions, key=lambda x: str(x)))
+
         print('Changed Condition Dict')
-        changed_conditiondict = aanalyzer.getChangedConditionsWithAssignments( signal )
-        print(sorted(changed_conditiondict.items(), key=lambda x:str(x[0])))
-    
+        changed_conditiondict = aanalyzer.getChangedConditionsWithAssignments(signal)
+        print(sorted(changed_conditiondict.items(), key=lambda x: str(x[0])))
+
         print('Unchanged Conditions')
-        unchanged_conditions = aanalyzer.getUnchangedConditions( signal )
-        print(sorted(unchanged_conditions, key=lambda x:str(x)))
+        unchanged_conditions = aanalyzer.getUnchangedConditions(signal)
+        print(sorted(unchanged_conditions, key=lambda x: str(x)))
+
 
 if __name__ == '__main__':
     main()

examples/example_ast_code.py

@@ -9,43 +9,45 @@
 import pyverilog.vparser.ast as vast
 from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
 
+
 def main():
-    datawid = vast.Parameter( 'DATAWID', vast.Rvalue(vast.IntConst('32')) )
-    params = vast.Paramlist( [datawid] )
-    clk = vast.Ioport( vast.Input('CLK') )
-    rst = vast.Ioport( vast.Input('RST') )
-    width = vast.Width( vast.IntConst('7'), vast.IntConst('0') )
-    led = vast.Ioport( vast.Output('led', width=width) )
-    ports = vast.Portlist( [clk, rst, led] )
-
-    width = vast.Width( vast.Minus(vast.Identifier('DATAWID'), vast.IntConst('1')), vast.IntConst('0') )
+    datawid = vast.Parameter('DATAWID', vast.Rvalue(vast.IntConst('32')))
+    params = vast.Paramlist([datawid])
+    clk = vast.Ioport(vast.Input('CLK'))
+    rst = vast.Ioport(vast.Input('RST'))
+    width = vast.Width(vast.IntConst('7'), vast.IntConst('0'))
+    led = vast.Ioport(vast.Output('led', width=width))
+    ports = vast.Portlist([clk, rst, led])
+
+    width = vast.Width(vast.Minus(vast.Identifier('DATAWID'),
+                                  vast.IntConst('1')), vast.IntConst('0'))
     count = vast.Reg('count', width=width)
 
     assign = vast.Assign(
-        vast.Lvalue(vast.Identifier('led')), 
+        vast.Lvalue(vast.Identifier('led')),
         vast.Rvalue(
             vast.Partselect(
-                vast.Identifier('count'), # count
-                vast.Minus(vast.Identifier('DATAWID'), vast.IntConst('1')), # [DATAWID-1:
-                vast.Minus(vast.Identifier('DATAWID'), vast.IntConst('8'))))) # :DATAWID-8]
+                vast.Identifier('count'),  # count
+                vast.Minus(vast.Identifier('DATAWID'), vast.IntConst('1')),  # [DATAWID-1:
+                vast.Minus(vast.Identifier('DATAWID'), vast.IntConst('8')))))  # :DATAWID-8]
 
     sens = vast.Sens(vast.Identifier('CLK'), type='posedge')
-    senslist = vast.SensList([ sens ])
+    senslist = vast.SensList([sens])
 
     assign_count_true = vast.NonblockingSubstitution(
         vast.Lvalue(vast.Identifier('count')),
         vast.Rvalue(vast.IntConst('0')))
-    if0_true = vast.Block([ assign_count_true ])
+    if0_true = vast.Block([assign_count_true])
 
     # count + 1
     count_plus_1 = vast.Plus(vast.Identifier('count'), vast.IntConst('1'))
     assign_count_false = vast.NonblockingSubstitution(
         vast.Lvalue(vast.Identifier('count')),
         vast.Rvalue(count_plus_1))
-    if0_false = vast.Block([ assign_count_false ])
+    if0_false = vast.Block([assign_count_false])
 
     if0 = vast.IfStatement(vast.Identifier('RST'), if0_true, if0_false)
-    statement = vast.Block([ if0 ])
+    statement = vast.Block([if0])
 
     always = vast.Always(senslist, statement)
 
@@ -55,10 +57,11 @@ def main():
     items.append(always)
 
     ast = vast.ModuleDef("top", params, ports, items)
-    
+
     codegen = ASTCodeGenerator()
     rslt = codegen.visit(ast)
     print(rslt)
 
+
 if __name__ == '__main__':
     main()

examples/example_codegen.py

@@ -7,36 +7,38 @@
 # the next line can be removed after installation
 sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.abspath(__file__))))
 
-import pyverilog.utils.version
+import pyverilog
 from pyverilog.vparser.parser import VerilogCodeParser
 from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
 
+
 def main():
     INFO = "Code converter from AST"
-    VERSION = pyverilog.utils.version.VERSION
+    VERSION = pyverilog.__version__
     USAGE = "Usage: python example_codegen.py file ..."
 
     def showVersion():
         print(INFO)
         print(VERSION)
         print(USAGE)
         sys.exit()
-    
+
     optparser = OptionParser()
-    optparser.add_option("-v","--version",action="store_true",dest="showversion",
-                         default=False,help="Show the version")
-    optparser.add_option("-I","--include",dest="include",action="append",
-                         default=[],help="Include path")
-    optparser.add_option("-D",dest="define",action="append",
-                         default=[],help="Macro Definition")
+    optparser.add_option("-v", "--version", action="store_true", dest="showversion",
+                         default=False, help="Show the version")
+    optparser.add_option("-I", "--include", dest="include", action="append",
+                         default=[], help="Include path")
+    optparser.add_option("-D", dest="define", action="append",
+                         default=[], help="Macro Definition")
     (options, args) = optparser.parse_args()
 
     filelist = args
     if options.showversion:
         showVersion()
 
     for f in filelist:
-        if not os.path.exists(f): raise IOError("file not found: " + f)
+        if not os.path.exists(f):
+            raise IOError("file not found: " + f)
 
     if len(filelist) == 0:
         showVersion()
@@ -52,5 +54,6 @@ def showVersion():
     rslt = codegen.visit(ast)
     print(rslt)
 
+
 if __name__ == '__main__':
     main()