3.0

What's Changed

• Adapt FPGA loading to use the FPGA manager by @EmilioPeJu in #47
• numerous changes and restructuring for target independent build by @glennchid in #33
• Python3 changes by @thomascobb in #52
• Moving slowFPGA build to separate repo by @glennchid in #53
• Python 3 Udpate by @MichaelStubbings in #55
• pcap: fix driver overrun issue caused by the last 2 IRQs too close by @shu-soleil in #57
• pcap: avoid pcap_fsm jumping in ACTV/DMA states before last IRQ by @shu-soleil in #59
• Add CI by @MichaelStubbings in #54
• Changed target IO definitions by @tomtrafford in #66
• add pcap_std_dev option in target.ini for top_defines entry by @shu-soleil in #65
• Add support for SoC Mercury XU5 on base board ST1 by @EmilioPeJu in #67
• Building dtc from source and removing binary blob by @glennchid in #70
• Adding dtc sources to the CU dependencies by @glennchid in #71
• Automatically add target specific modules by @EmilioPeJu in #72
• Allow passing fpga options in the application file by @EmilioPeJu in #73
• sfp_udpontrig module update to support ping protocol by @shu-soleil in #46
• Finedelay by @EmilioPeJu in #76
• Fix release action by @MichaelStubbings in #74
• Add sum^2 calculation for PCAP module when the pcap_std_dev option is set by @shu-soleil in #68
• modify single_test.tcl to add checks on the testbench ending state by @shu-soleil in #85
• finedelay: register ddr outputs to meet timing constraints by @EmilioPeJu in #90
• Fixed the PCAP python simulation tests. by @tomtrafford in #92
• Fix PCAP hdl test error and modify PCAP Sum^2 timing sections by @shu-soleil in #94
• Containerisation of Continuous Integration by @Araneidae in #78
• Change IP build to global synthesis rather than out-of-context (OOC) by @glennchid in #98
• add OUT_MODE param to counter for rate meter application by @shu-soleil in #96
• add WIDTH param to CLOCK for issue #95 by @shu-soleil in #97
• Remove app files from targets to avoid duplication by @EmilioPeJu in #99
• Fixed incorrect commands in testing docs by @adhowell in #100
• Added top_defines_gen template and made top_defines non-templated by @adhowell in #101
• Optional finedelay by @EmilioPeJu in #102
• Add PCAP interrupt on PCAP.ENABLE high when armed and enabled by @EmilioPeJu in #110
• Use VHDL2008 by @EmilioPeJu in #112
• Fix for USB on PandABox by @glennchid in #114
• Changes to build system to only generate IP required for App by @glennchid in #116
• Autogen fixes by @EmilioPeJu in #120
• Clocking changes to allow fine delay and recovered clock by @glennchid in #113
• Vivado2022.2 upgrade by @glennchid in #117
• Adding -quiet flag to prevent error with qdec build by @glennchid in #124
• Removed 'dls' from sfp_dls_eventr by @tomtrafford in #128
• Add double table sequencer feature by @EmilioPeJu in #130
• Sequencer block modifications by @EmilioPeJu in #131
• Counter module: add TRIG_EDGE param by @shu-soleil in #132
• pcap: simplify pcap_dma by @EmilioPeJu in #137
• Simplify axi_lite_slave and make it faster by @EmilioPeJu in #139
• Fixed typo in address of outenc write strobe by @adhowell in #140
• Added support for write extensions by @Araneidae in #79
• Write eeprom feature by @EmilioPeJu in #153
• Tidy-up of encoders and slow interface by @glennchid in #142
• Sync picxo by @glennchid in #160
• Remove executable flags from files which cannot safely be executed by @Araneidae in #157
• Update common/templates/registers_server to match current server version by @Araneidae in #156
• Rename SAMPLES to GATE_DURATION by @Araneidae in #155
• Sync protocol changes by @glennchid in #138
• Remove over-riding of ctrl block ack ports where feasible by @glennchid in #162
• Various PandA-sync fixes by @glennchid in #164
• Update FPGA boot files release by @tomtrafford in #163

Full Changelog: 2.1...3.0