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Ssi splitter #81

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Ssi splitter #81

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Commits on Apr 13, 2021

  1. Changes for DCARD_MONITOR+CONTROL 

    * Change polarity of CLK_OUT RE#/DE control signal
* Always tri-state B_IN for new DCARD mode
* MUX on sniffer CLK_IN between CLK_IN and CLK_OUT xcvr
    @glennchid
    glennchid committed Apr 13, 2021
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  2. Remove unnecessary logic driving Bs0 (B_OUT) tri-state control

    @glennchid
    glennchid committed Apr 13, 2021
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  3. Change default case for outenc to disable all xcvrs

    @glennchid
    glennchid committed Apr 13, 2021
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Commits on Apr 14, 2021

  1. Fix INENC MON+CTRL to use sniffer signals 

    * renamd DCARD_MON_CTRL constant
    @glennchid
    glennchid committed Apr 14, 2021
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Commits on Apr 18, 2021

  1. Encoder changes to support bi-directional protocols

    @glennchid
    glennchid committed Apr 18, 2021
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  2. Fix missing signal in function call

    @glennchid
    glennchid committed Apr 18, 2021
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  3. Fix INENC termination for MONITOR mode to always OFF 

    * INENC data signal will be terminated by the encoder for the MONITOR card
    @glennchid
    glennchid committed Apr 18, 2021
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Commits on May 10, 2021

  1. Added Mon+Ctrl Dcard type to encodes block.ini file

    @glennchid
    glennchid committed May 10, 2021
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Commits on Jul 12, 2021

  1. Added Chipscope ILA to Zynq encoders block

    @glennchid
    glennchid committed Jul 12, 2021
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Commits on Sep 21, 2021

  1. Added debounce controls to ssi-sniffer module 

    * Also added second ILA to the sssi-sniffer
    @glennchid
    glennchid committed Sep 21, 2021
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Commits on Sep 29, 2021

  1. Changes for SSI-splitter mode

    @glennchid
    glennchid committed Sep 29, 2021
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Commits on Oct 4, 2021

  1. Added MUX to OUTENC clock going to the bitbus

    @glennchid
    glennchid committed Oct 4, 2021
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  2. Removed ASYNC_REG property from delay_filter and added IDDR sync

    @glennchid
    glennchid committed Oct 4, 2021
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  3. Removing unnecessary logic from encoders module 

    * This logic did not what was expected and would be ignored by
* the Slow FPGA in Monitor Card mode.
    @glennchid
    glennchid committed Oct 4, 2021
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  4. Revert "Remove unnecessary logic driving Bs0 (B_OUT) tri-state control" 

    This reverts commit 302994b.
    @glennchid
    glennchid committed Oct 4, 2021
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  5. Minor tidy-up

    @glennchid
    glennchid committed Oct 4, 2021
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