Fmc i2c

apps/xu5_st1-fmc_x4sfp.app.ini

@@ -0,0 +1,33 @@
+[.]
+description:
+    Standard set of PandABox blocks with:
+        - FMC x4SFP
+        - PandA synchroniser on all MGTs
+target: xu5_st1
+options: !pcap_std_dev
+includes: common_soft_blocks.include.ini
+
+[FMC_X4SFP]
+module: fmc_x4sfp
+
+[SFP1_SYNC]
+module: sfp_panda_sync
+ini: sfp_panda_sync_us.block.ini
+site: fmc_mgt 1
+
+[SFP2_SYNC]
+module: sfp_panda_sync
+ini: sfp_panda_sync_us.block.ini
+site: fmc_mgt 2
+
+[SFP3_SYNC]
+module: sfp_panda_sync
+ini: sfp_panda_sync_us.block.ini
+site: fmc_mgt 3
+
+[SFP4_SYNC]
+module: sfp_panda_sync
+ini: sfp_panda_sync_us.block.ini
+site: fmc_mgt 4
+
+

common/hdl/defines/interface_types.vhd

@@ -14,6 +14,12 @@ package interface_types is
         FMC_CLK0_M2C_N  : std_logic;
         FMC_CLK1_M2C_P  : std_logic;
         FMC_CLK1_M2C_N  : std_logic;
+        FMC_I2C_SDA_in  : std_logic;
+        FMC_I2C_SDA_out : std_logic;
+        FMC_I2C_SDA_tri : std_logic;
+        FMC_I2C_SCL_in  : std_logic;
+        FMC_I2C_SCL_out : std_logic;
+        FMC_I2C_SCL_tri : std_logic;
       end record FMC_interface;
 
     view FMC_Module of FMC_interface is
@@ -24,6 +30,13 @@ package interface_types is
         FMC_CLK0_M2C_N  : inout;
         FMC_CLK1_M2C_P  : in;
         FMC_CLK1_M2C_N  : in;
+        FMC_I2C_SDA_in  : out;
+        FMC_I2C_SDA_out : in;
+        FMC_I2C_SDA_tri : in;
+        FMC_I2C_SCL_in  : out;
+        FMC_I2C_SCL_out : in;
+        FMC_I2C_SCL_tri : in;
+
     end view FMC_Module;
 
     constant FMC_init : FMC_interface;
@@ -92,7 +105,13 @@ package body interface_types is
                                             FMC_CLK0_M2C_P => 'Z',
                                             FMC_CLK0_M2C_N => 'Z',
                                             FMC_CLK1_M2C_P => '0',
-                                            FMC_CLK1_M2C_N => '0');
+                                            FMC_CLK1_M2C_N => '0',
+                                            FMC_I2C_SDA_in => '0',
+                                            FMC_I2C_SDA_out => '0',
+                                            FMC_I2C_SDA_tri => '1',
+                                            FMC_I2C_SCL_in => '0',
+                                            FMC_I2C_SCL_out => '0',
+                                            FMC_I2C_SCL_tri => '1');
 
     constant MGT_init : MGT_interface := (  SFP_LOS => '0',
                                             GTREFCLK => '0',

modules/fmc_x4sfp/const/fmc_x4sfp.xdc

@@ -0,0 +1,6 @@
+# -------------------------------------------------------------------
+# FMC Clock Timing Constraints
+# -------------------------------------------------------------------
+create_clock -period 6.400  [get_ports FMC_CLK0_M2C_P[0]]
+create_clock -period 6.400  [get_ports FMC_CLK1_M2C_P[0]]
+

modules/fmc_x4sfp/const/fmc_x4sfp_impl.xdc

@@ -0,0 +1,12 @@
+# -------------------------------------------------------------------
+# Define asynchronous clocks
+# -------------------------------------------------------------------
+set_clock_groups -asynchronous -group FMC_CLK0_M2C_P[0]
+set_clock_groups -asynchronous -group FMC_CLK1_M2C_P[0]
+
+# -------------------------------------------------------------------
+# Override Differential Pairs' IOSTANDARD
+# -------------------------------------------------------------------
+set_property IOSTANDARD LVDS    [get_ports FMC_CLK0_M2C_P[0]]
+set_property IOSTANDARD LVDS    [get_ports FMC_CLK1_M2C_P[0]]
+

modules/fmc_x4sfp/fmc_x4sfp.block.ini

@@ -3,6 +3,7 @@ description: HPC-FMC card with 4 SFP+ ports
 entity: fmc_x4sfp
 type: io
 interfaces: FMC
+constraints: const/fmc_x4sfp.xdc const/fmc_x4sfp_impl.xdc
 extra_interface: fmc_mgt: mgt 4
 
 [FMC_PRSNT]
@@ -12,3 +13,20 @@ description: FMC present
 1: FMC Connected
 2: FMC_PRSNT not supported
 
+[FMC_I2C_MUX]
+description: MUX selector for FMC I2C
+type: param enum
+0: SFP1
+1: SFP2
+2: SFP3
+3: SFP4
+4: Si570
+
+[FMC_CLK0]
+type: read
+description: FMC CLK0 clock freq (if supported)
+
+[FMC_CLK1]
+type: read
+description: FMC CLK1 clock freq (if supported)
+

modules/fmc_x4sfp/hdl/fmc_x4sfp_wrapper.vhd

@@ -1,5 +1,6 @@
 library ieee;
 use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
 
 use work.support.all;
 use work.top_defines.all;
@@ -29,14 +30,107 @@ end fmc_x4sfp_wrapper;
 
 architecture rtl of fmc_x4sfp_wrapper is
 
+constant NUM_I2C_CHANS : natural := 5;
+
 signal FMC_PRSNT_DW     : std_logic_vector(31 downto 0);
+signal FMC_I2C_MUX_VEC  : std_logic_vector(31 downto 0);
+signal FMC_I2C_MUX      : integer range 0 to NUM_I2C_CHANS-1;
+signal FMC_CLK0_M2C     : std_logic;
+signal FMC_CLK1_M2C     : std_logic;
+signal FREQ_VAL         : std32_array(1 downto 0);
+signal test_clocks      : std_logic_vector(1 downto 0);
+signal FMC_SDA_DEMUX    : std_logic_vector(NUM_I2C_CHANS-1 downto 0);
+signal FMC_SCL_DEMUX    : std_logic_vector(NUM_I2C_CHANS-1 downto 0);
 
 begin
 
 ---------------------------------------------------------------------------
 -- FMC CSR Interface
 ---------------------------------------------------------------------------
 FMC_PRSNT_DW <= ZEROS(30) & FMC.FMC_PRSNT;
+FMC_I2C_MUX <= to_integer(unsigned(FMC_I2C_MUX_VEC));
+
+-- Mux/Demux the SFP I2C for the HiTechGlobal FMC (HTG-FMC-x4-SFP)
+-- Note that SFP numbering is reversed wrt to the FMC DP numbering
+-- S0 SDA/SCL on LA00_N_CC/LA00_P_CC --- DP3
+-- S1 SDA/SCL on LA01_N_CC/LA01_P_CC --- DP2
+-- S2 SDA/SCL on LA02_N/LA02_P       --- DP1
+-- S3 SDA/SCL on LA04_N/LA04_P       --- DP0   
+-- OSC SDA/SCL on LA05_N/LA05_P
+-- OSC_EN on LA03_N and CLK_SEL on LA03_P
+-- Note CLK_SEL needs to be set to '0' as incorrectly pulled high on card
+
+FMC.FMC_LA_P(3) <= '0'; -- CLK_SEL
+FMC.FMC_LA_N(3) <= '1'; -- OSC_EN
+
+FMC.FMC_LA_N(0) <= FMC_SDA_DEMUX(3);
+FMC.FMC_LA_P(0) <= FMC_SCL_DEMUX(3);
+FMC.FMC_LA_N(1) <= FMC_SDA_DEMUX(2);
+FMC.FMC_LA_P(1) <= FMC_SCL_DEMUX(2);
+FMC.FMC_LA_N(2) <= FMC_SDA_DEMUX(1);
+FMC.FMC_LA_P(2) <= FMC_SCL_DEMUX(1);
+FMC.FMC_LA_N(4) <= FMC_SDA_DEMUX(0);
+FMC.FMC_LA_P(4) <= FMC_SCL_DEMUX(0);
+FMC.FMC_LA_N(5) <= FMC_SDA_DEMUX(4);
+FMC.FMC_LA_P(5) <= FMC_SCL_DEMUX(4);
+
+-- Mux/Demux for FMC I2C
+
+FMC.FMC_I2C_SDA_in <= FMC_SDA_DEMUX(FMC_I2C_MUX) when 
+    FMC_I2C_MUX < NUM_I2C_CHANS else FMC_SDA_DEMUX(NUM_I2C_CHANS-1);
+FMC.FMC_I2C_SCL_in <= FMC_SCL_DEMUX(FMC_I2C_MUX) when 
+    FMC_I2C_MUX < NUM_I2C_CHANS else FMC_SCL_DEMUX(NUM_I2C_CHANS-1);
+
+FMC_DEMUX_GEN: for chan in 0 to NUM_I2C_CHANS-1 generate
+    FMC_SDA_DEMUX(chan) <= '0' when
+        FMC_I2C_MUX = chan and FMC.FMC_I2C_SDA_tri = '0' and FMC.FMC_I2C_SDA_out = '0'
+        else 'Z';
+    FMC_SCL_DEMUX(chan) <= '0' when
+        FMC_I2C_MUX = chan and FMC.FMC_I2C_SCL_tri = '0' and FMC.FMC_I2C_SCL_out = '0'
+        else 'Z';
+end generate;
+
+
+---------------------------------------------------------------------------
+-- FMC Mezzanine Clocks
+---------------------------------------------------------------------------
+IBUFGDS_CLK0 : IBUFGDS
+generic map (
+    DIFF_TERM   => TRUE,
+    IOSTANDARD  => "LVDS"
+)
+port map (
+    O           => FMC_CLK0_M2C,
+    I           => FMC.FMC_CLK0_M2C_P,
+    IB          => FMC.FMC_CLK0_M2C_N
+);
+
+IBUFGDS_CLK1 : IBUFGDS
+generic map (
+    DIFF_TERM   => TRUE,
+    IOSTANDARD  => "LVDS"
+)
+port map (
+    O           => FMC_CLK1_M2C,
+    I           => FMC.FMC_CLK1_M2C_P,
+    IB          => FMC.FMC_CLK1_M2C_N
+);
+
+---------------------------------------------------------------------------
+-- FMC Clocks Frequency Counter
+---------------------------------------------------------------------------
+
+test_clocks(0) <= FMC_CLK0_M2C;
+test_clocks(1) <= FMC_CLK1_M2C;
+
+freq_counter_inst : entity work.freq_counter
+generic map ( NUM => 2)
+port map (
+    refclk          => clk_i,
+    reset           => reset_i,
+    test_clocks     => test_clocks,
+    freq_out        => FREQ_VAL
+);
 
 fmc_x4sfp_inst : entity work.fmc_x4sfp_ctrl
 port map(
@@ -46,6 +140,9 @@ port map(
     pos_bus_i => pos_bus_i,
     -- Block Parameters
     FMC_PRSNT           => FMC_PRSNT_DW,
+    FMC_I2C_MUX         => FMC_I2C_MUX_VEC,
+    FMC_CLK0            => FREQ_VAL(0),
+    FMC_CLK1            => FREQ_VAL(1),
     -- Memory Bus Interface
     read_strobe_i       => read_strobe_i,
     read_address_i      => read_address_i(BLK_AW-1 downto 0),
@@ -58,3 +155,4 @@ port map(
     write_ack_o         => write_ack_o
 );
 end rtl;
+

modules/sfp_panda_sync/hdl/sfp_panda_sync_wrapper.vhd

@@ -78,6 +78,7 @@ signal POSOUT4            : std_logic_vector(31 downto 0);
 signal BITOUT             : std_logic_vector(7 downto 0);
 signal LINKUP             : std_logic_vector(31 downto 0);
 signal SYNC_RESET         : std_logic;
+signal MGT_RESET          : std_logic;
 signal TXN                : std_logic;
 signal TXP                : std_logic;
 signal health             : std_logic_vector(31 downto 0);
@@ -197,6 +198,7 @@ sfp_panda_sync_mgt_interface_inst : entity work.sfp_panda_sync_mgt_interface
     port map(
         GTREFCLK_i        => MGT.GTREFCLK,
         SYNC_RESET_i      => SYNC_RESET,
+        MGT_RESET_i       => MGT_RESET,
         sysclk_i          => clk_i,
         rxp_i             => MGT.RXP_IN,
         rxn_i             => MGT.RXN_IN,
@@ -235,6 +237,8 @@ sfp_panda_sync_ctrl_inst : entity work.sfp_panda_sync_ctrl
         IN_SYNC_RESET_wstb  => SYNC_RESET,
         IN_HEALTH           => health,
         IN_ERR_CNT          => err_cnt_smpld,
+        OUT_MGT_RESET       => open,
+        OUT_MGT_RESET_wstb  => MGT_RESET,
         OUT_BIT1_from_bus   => BITOUT1,
         OUT_BIT2_from_bus   => BITOUT2,
         OUT_BIT3_from_bus   => BITOUT3,

modules/sfp_panda_sync/hdl_zynq/sfp_panda_sync_mgt_interface.vhd

@@ -13,6 +13,7 @@ entity sfp_panda_sync_mgt_interface is
 
     port (GTREFCLK_i        : in  std_logic;
           SYNC_RESET_i      : in  std_logic;
+          MGT_RESET_i       : in  std_logic;
           sysclk_i          : in  std_logic;
           rxp_i             : in  std_logic;
           rxn_i             : in  std_logic;
@@ -53,7 +54,8 @@ signal GT0_RX_FSM_RESET_DONE_sync   : std_logic;
 signal gt0_txresetdone_sync         : std_logic;
 signal gt0_rxresetdone_sync         : std_logic;
 signal init_rst                     : std_logic;
-signal mgt_rst                      : std_logic;
+signal mgt_soft_rst                 : std_logic;
+signal mgt_hard_rst                 : std_logic;
 
 -- PICXO signals
 
@@ -140,7 +142,8 @@ begin
     end if;
 end process;
 
-mgt_rst <= SYNC_RESET_i or init_rst;
+mgt_soft_rst <= SYNC_RESET_i or init_rst;
+mgt_hard_rst <= MGT_RESET_i or init_rst;
 
 -- ####################################################################################### --
 -- clks
@@ -155,8 +158,8 @@ mgt_rst <= SYNC_RESET_i or init_rst;
 sfp_panda_sync_i : entity work.sfp_panda_sync
     port map(
         SYSCLK_IN                       => GTREFCLK_i,
-        SOFT_RESET_TX_IN                => init_rst,
-        SOFT_RESET_RX_IN                => mgt_rst,
+        SOFT_RESET_TX_IN                => mgt_hard_rst,
+        SOFT_RESET_RX_IN                => mgt_soft_rst,
         DONT_RESET_ON_DATA_ERROR_IN     => '0',
         GT0_TX_FSM_RESET_DONE_OUT       => GT0_TX_FSM_RESET_DONE,
         GT0_RX_FSM_RESET_DONE_OUT       => GT0_RX_FSM_RESET_DONE,

modules/sfp_panda_sync/hdl_zynqmp/sfp_panda_sync_mgt_interface.vhd

@@ -12,6 +12,7 @@ entity sfp_panda_sync_mgt_interface is
     port (
         GTREFCLK_i        : in  std_logic;
         SYNC_RESET_i      : in  std_logic;
+        MGT_RESET_i       : in  std_logic;
         sysclk_i          : in  std_logic;
         rxp_i             : in  std_logic;
         rxn_i             : in  std_logic;
@@ -99,7 +100,8 @@ signal RX_PMA_RESET_DONE_OUT_sync   : std_logic;
 signal gtwiz_reset_rx_done_out_sync : std_logic;
 signal gtwiz_reset_tx_done_out_sync : std_logic;
 signal init_rst                     : std_logic;
-signal mgt_rst                      : std_logic;
+signal mgt_soft_rst                 : std_logic;
+signal mgt_hard_rst                 : std_logic;
 
 signal rxctrl0_int                  : STD_LOGIC_VECTOR(15 DOWNTO 0);
 signal rxctrl1_int                  : STD_LOGIC_VECTOR(15 DOWNTO 0);
@@ -171,7 +173,8 @@ begin
     end if;
 end process;
 
-mgt_rst <= SYNC_RESET_i or init_rst;
+mgt_soft_rst <= SYNC_RESET_i or init_rst;
+mgt_hard_rst <= MGT_RESET_i or init_rst;
 
 --======================================================================
 --   CORE INSTANCE
@@ -191,11 +194,11 @@ sfp_panda_sync_us_i : sfp_panda_sync_us
     gtwiz_userclk_rx_usrclk2_out => open,
     gtwiz_userclk_rx_active_out => open,
     gtwiz_reset_clk_freerun_in(0) => sysclk_i,
-    gtwiz_reset_all_in(0) => init_rst,
+    gtwiz_reset_all_in(0) => mgt_hard_rst,
     gtwiz_reset_tx_pll_and_datapath_in(0) => '0',
     gtwiz_reset_tx_datapath_in(0) => '0',
     gtwiz_reset_rx_pll_and_datapath_in(0) => '0',
-    gtwiz_reset_rx_datapath_in(0) => mgt_rst,
+    gtwiz_reset_rx_datapath_in(0) => mgt_soft_rst,
     gtwiz_reset_rx_cdr_stable_out => open,
     gtwiz_reset_tx_done_out(0) => gtwiz_reset_tx_done_out,
     gtwiz_reset_rx_done_out(0) => gtwiz_reset_rx_done_out,

modules/sfp_panda_sync/sfp_panda_sync.block.ini

@@ -77,6 +77,10 @@ description: Error status
 type: read uint
 description: Number of not-in-table or disparity errors
 
+[OUT.MGT_RESET]
+type: write action
+description: MGT hard reset
+
 [OUT.BIT1]
 type: bit_mux
 description: SFP panda sync bit 1 output 

modules/sfp_panda_sync/sfp_panda_sync_us.block.ini

@@ -77,6 +77,10 @@ description: Error status
 type: read uint
 description: Number of not-in-table or disparity errors
 
+[OUT.MGT_RESET]
+type: write action
+description: MGT hard reset
+
 [OUT.BIT1]
 type: bit_mux
 description: SFP panda sync bit 1 output