Fix for SSI and BiSS encoder modules to correctly detect encoder loss

[glennchid]

• Encoder loss deduced from serial data from encoder not clock
• Loss detection common to master and sniffer
• For BiSS, just check for clock at startup as CRC will check data
• integrity. Serial clock is needed to interpret data frame.

CONN signal for SSI and BISS sniffer modules was showing as 1 (connected) when nothing was plugged into DB9 connectors.
This was because the 'serial_link_detect' module was looking for the clock signal staying high for 5us to verify the link, and then checking for rising edges during the active period, following the first falling edge. The RS-485 line drivers read high on the line when nothing is connected, so it satisfied the first condition and the initial falling edge for the frame never arrives.

For SSI_master the CONN signal was previously hard-wired to '0'.

Changed both SSI_master and SSI_sniffer to look at the data signal (not the clock) and check for initial high level, and subsequent low approximately mid-way through the 20 us timeout period. Unfortunately, this still requires the serial clock (to define the frame), so if the clock goes away, CONN will stay high. This is not a problem for the SSI_master as the clock is generated by the FPGA (so can't go away) and for the sniffer this would represent the PMAC being disconnected (so it can not be controlling anything).

For BISS_sniffer, we now just check for the serial clock going low at the start of a frame (avoiding CONN falsely reading high when disconnected). The data integrity is checked by the CRC. If the clock later goes away, CONN will remain high but the same argument as for SSI_sniffer applies.

I would like to have this checked with actual encoders. I have only been able to check behaviour when nothing is connected.

Closes #89