Merge pull request #39 from valerixb/encoder_gray

Encoder gray + signed/unsigned

common/hdl/defines/support.vhd

@@ -4,6 +4,11 @@ use ieee.numeric_std.all;
 
 package support is
 
+constant c_UNSIGNED_BINARY_ENCODING  : std_logic_vector(1 downto 0) := "00";
+constant c_UNSIGNED_GRAY_ENCODING    : std_logic_vector(1 downto 0) := "01";
+constant c_SIGNED_BINARY_ENCODING    : std_logic_vector(1 downto 0) := "10";
+constant c_SIGNED_GRAY_ENCODING      : std_logic_vector(1 downto 0) := "11";
+
 --
 -- Functions
 --

common/hdl/serial_engine_rx.vhd

@@ -119,6 +119,7 @@ generic map (
 port map (
     clk_i           => clk_i,
     reset_i         => reset_i,
+    ENCODING        => "00",
     enable_i        => shift_enabled,
     clock_i         => shift_clock,
     data_i          => shift_data,

common/hdl/shifter_in.vhd

@@ -19,24 +19,25 @@ use work.support.all;
 
 entity shifter_in is
 generic (
-    DW              : natural := 48
+    DW               : natural := 48
 );
 port (
-    clk_i           : in  std_logic;
-    reset_i         : in  std_logic;
+    clk_i            : in  std_logic;
+    reset_i          : in  std_logic;
+    ENCODING         : in  std_logic_vector(1 downto 0);
     -- Physical SSI interface
-    enable_i        : in  std_logic;
-    clock_i         : in  std_logic;
-    data_i          : in  std_logic;
+    enable_i         : in  std_logic;
+    clock_i          : in  std_logic;
+    data_i           : in  std_logic;
     -- Block outputs
-    data_o          : out std_logic_vector(DW-1 downto 0);
-    data_valid_o    : out std_logic
+    data_o           : out std_logic_vector(DW-1 downto 0);
+    data_valid_o     : out std_logic
 );
 end shifter_in;
 
 architecture rtl of shifter_in is
 
-signal smpl_hold    : std_logic_vector(DW-1 downto 0);
+signal smpl_hold   : std_logic_vector(DW-1 downto 0);
 signal valid_prev  : std_logic;
 signal valid_fall  : std_logic;
 
@@ -66,7 +67,11 @@ begin
             -- Shift data when enabled.
             elsif (enable_i = '1') then
                 if (clock_i = '1') then
-                    smpl_hold <= smpl_hold(DW-2 downto 0) & data_i;
+                    if ((ENCODING=c_UNSIGNED_BINARY_ENCODING) or (ENCODING=c_SIGNED_BINARY_ENCODING)) then
+                        smpl_hold <= smpl_hold(DW-2 downto 0) & data_i;
+                    else
+                        smpl_hold <= smpl_hold(DW-2 downto 0) & (data_i xor smpl_hold(0));
+                    end if;
                 end if;
             end if;
         end if;

common/templates/block_wrapper.vhd.jinja2

@@ -109,7 +109,7 @@ begin
     {% elif field in filter_fields("pos_mux") %}
             {{ pad(field.name+"_from_bus") }} => {{ field.name }}(I),
     {% else %}
-		{% for register in field.numbered_registers() %}
+        {% for register in field.numbered_registers() %}
             {{ pad(register.name) }} => {{ register.name }}(I),
             {% if "read" not in field.type %}
             {{ pad(register.name + "_wstb") }} => {{ register.name }}_wstb(I),
@@ -133,11 +133,11 @@ begin
         {{ entity }} : entity work.{{ entity }}
         port map (
 {% for field in fields %}
-	{% if field in filter_fields("bit_mux") %}
+    {% if field in filter_fields("bit_mux") %}
             {{ pad(field.name +"_i") }} => {{ field.name }}(I)(0),
-	{% elif field in filter_fields("pos_mux") %}
+    {% elif field in filter_fields("pos_mux") %}
             {{ pad(field.name +"_i") }} => {{ field.name }}(I),
-	{% elif field in filter_fields(".*_out") %}
+    {% elif field in filter_fields(".*_out") %}
             {{ pad(field.name + "_o") }} => {{ field.name }}_o(I),
     {% else %}
         {% for register in field.numbered_registers() %}

common/templates/hdl_timing.v.jinja2

@@ -15,10 +15,10 @@ always #4 clk_i = ~clk_i;
     {% if field.type == "bit_mux" %}
 reg         {{ field.name }};
     {% else %}
-	    {% for register in field.numbered_registers() %}
+        {% for register in field.numbered_registers() %}
 reg  [31:0] {{ register.name }};
-	    {% endfor %}
-	{% endif %}
+        {% endfor %}
+    {% endif %}
 {% endfor %}
 
 // Outputs

common/templates/pcap_hdl_timing.v.jinja2

@@ -37,15 +37,15 @@ reg              reset = 1;
     {% if field.type == "bit_mux" %}
 reg         {{ field.name }};
     {% else %}
-	    {% for register in field.registers %}
-	        {% if register.number >= 0 %}
+        {% for register in field.registers %}
+            {% if register.number >= 0 %}
 reg  [31:0] {{ register.name }};
-			{% endif %}
-	    {% endfor %}
-	    {% if field.type == "time" %}
+            {% endif %}
+        {% endfor %}
+        {% if field.type == "time" %}
 wire [47:0] {{ field.name }};
-	    {% endif %}
-	{% endif %}
+        {% endif %}
+    {% endif %}
 {% endfor %}
 
 // Outputs
@@ -73,7 +73,7 @@ reg         {{ field.name }}_err;   //Error signal
         {% for register in field.registers %}
             {% if register.number >= 0 %}
 reg         {{ register.name }}_wstb;
-			{% endif %}
+            {% endif %}
         {% endfor %}
         {% if field.type == "time" %}
 wire        {{ field.name }}_wstb;

common/templates/top_defines.vhd.jinja2

@@ -115,7 +115,7 @@ type SFP_output_interface is
   record
     TXN_OUT     : std_logic;
     TXP_OUT     : std_logic;
-	EVR_REC_CLK : std_logic;
+    EVR_REC_CLK : std_logic;
     LINK_UP     : std_logic;
   end record SFP_output_interface;
 

modules/fmc_acq427/hdl/fmc_acq427_wrapper.vhd

@@ -30,14 +30,14 @@ port (
     bit_bus_i           : in  bit_bus_t;
     pos_bus_i           : in  pos_bus_t;
     -- Outputs to PosBus from FMC
-	in_val1_o				: out std32_array(0 downto 0);
-	in_val2_o				: out std32_array(0 downto 0);
-	in_val3_o				: out std32_array(0 downto 0);
-	in_val4_o				: out std32_array(0 downto 0);
-	in_val5_o				: out std32_array(0 downto 0);
-	in_val6_o				: out std32_array(0 downto 0);
-	in_val7_o				: out std32_array(0 downto 0);
-	in_val8_o				: out std32_array(0 downto 0);
+    in_val1_o               : out std32_array(0 downto 0);
+    in_val2_o               : out std32_array(0 downto 0);
+    in_val3_o               : out std32_array(0 downto 0);
+    in_val4_o               : out std32_array(0 downto 0);
+    in_val5_o               : out std32_array(0 downto 0);
+    in_val6_o               : out std32_array(0 downto 0);
+    in_val7_o               : out std32_array(0 downto 0);
+    in_val8_o               : out std32_array(0 downto 0);
     -- Outputs to BitBus from FMC
     in_ttl_o               : out std_logic_vector(0 downto 0);
     -- Memory Bus Interface

modules/fmc_loopback/hdl/fmc_loopback_wrapper.vhd

@@ -236,7 +236,7 @@ port map (
     FMC_CLK0            => FREQ_VAL(1),
     FMC_CLK1            => FREQ_VAL(2),
     EXT_CLK             => FREQ_VAL(3),
-	FMC_MAC_LO          => MAC_LO,
+    FMC_MAC_LO          => MAC_LO,
     FMC_MAC_HI          => MAC_HI,
     SOFT_RESET          => open,
     SOFT_RESET_WSTB     => SOFT_RESET,

modules/sfp_dls_eventr/hdl/sfp_dls_eventr_wrapper.vhd

@@ -17,7 +17,7 @@ port (
     -- System Bus
     bit_bus_i           : in  bit_bus_t;
     pos_bus_i           : in  pos_bus_t;
-	-- Outputs to BitBus from FMC
+    -- Outputs to BitBus from FMC
     bit1_o              : out std_logic_vector(0 downto 0);
     bit2_o              : out std_logic_vector(0 downto 0);
     bit3_o              : out std_logic_vector(0 downto 0);

old/tests/sim/panda_biss/bench/glbl.v

@@ -50,17 +50,17 @@ module glbl ();
     assign (weak1, weak0) PRLD = PRLD_int;
 
     initial begin
-	GSR_int = 1'b1;
-	PRLD_int = 1'b1;
-	#(ROC_WIDTH)
-	GSR_int = 1'b0;
-	PRLD_int = 1'b0;
+    GSR_int = 1'b1;
+    PRLD_int = 1'b1;
+    #(ROC_WIDTH)
+    GSR_int = 1'b0;
+    PRLD_int = 1'b0;
     end
 
     initial begin
-	GTS_int = 1'b1;
-	#(TOC_WIDTH)
-	GTS_int = 1'b0;
+    GTS_int = 1'b1;
+    #(TOC_WIDTH)
+    GTS_int = 1'b0;
     end
 
 endmodule

old/tests/sim/panda_slowctrl/bench/glbl.v

@@ -50,17 +50,17 @@ module glbl ();
     assign (weak1, weak0) PRLD = PRLD_int;
 
     initial begin
-	GSR_int = 1'b1;
-	PRLD_int = 1'b1;
-	#(ROC_WIDTH)
-	GSR_int = 1'b0;
-	PRLD_int = 1'b0;
+    GSR_int = 1'b1;
+    PRLD_int = 1'b1;
+    #(ROC_WIDTH)
+    GSR_int = 1'b0;
+    PRLD_int = 1'b0;
     end
 
     initial begin
-	GTS_int = 1'b1;
-	#(TOC_WIDTH)
-	GTS_int = 1'b0;
+    GTS_int = 1'b1;
+    #(TOC_WIDTH)
+    GTS_int = 1'b0;
     end
 
 endmodule

targets/PandABox/SlowFPGA/src/hdl/dcard_ctrl.vhd

@@ -70,8 +70,8 @@ begin
             return X"10";
         when "100"  => -- Pass
             return X"07";
-		when "101" => -- Data passthrough (same as SSI)
-			return X"28";
+        when "101" => -- Data passthrough (same as SSI)
+            return X"28";
         when others =>
             return X"00";
     end case;

targets/PandABox/blocks/inenc/inenc.block.ini

@@ -14,6 +14,14 @@ description: Type of absolute/incremental protocol
 2: BISS
 3: enDat
 
+[ENCODING]
+type: param enum
+description: Position encoding (for absolute encoders)
+0: Unsigned Binary
+1: Unsigned Gray
+2: Signed Binary
+3: Signed Gray
+
 [CLK_SRC]
 type: param enum
 description: Bypass/Pass Through encoder signals

targets/PandABox/blocks/outenc/outenc.block.ini

@@ -38,6 +38,14 @@ description: Type of absolute/incremental protocol
 4: ABZ Passthrough
 5: DATA Passthrough
 
+[ENCODING]
+type: param enum
+description: Position encoding (for absolute encoders)
+0: Unsigned Binary
+1: Unsigned Gray
+2: Signed Binary
+3: Signed Gray
+
 [BITS]
 type: param uint 32
 description: Number of bits

targets/PandABox/hdl/biss_master.vhd

@@ -10,6 +10,7 @@ entity biss_master is
 port(
     clk_i        : in  std_logic;
     reset_i      : in  std_logic;
+    ENCODING     : in  std_logic_vector(1 downto 0);
     BITS         : in  std_logic_vector(7 downto 0);
     link_up_o    : out std_logic;
     health_o     : out  std_logic_vector(31 downto 0);
@@ -385,6 +386,7 @@ generic map (
 port map (
     clk_i           => clk_i,
     reset_i         => reset_i,
+    ENCODING        => ENCODING,
     enable_i        => data_enable_i,
     clock_i         => biss_sck_rising_edge,
     data_i          => biss_dat_i,
@@ -401,6 +403,7 @@ generic map (
 port map (
     clk_i           => clk_i,
     reset_i         => reset_i,
+    ENCODING        => "00",
     enable_i        => nEnW_enable_i,
     clock_i         => biss_sck_rising_edge,
     data_i          => biss_dat_i,
@@ -417,6 +420,7 @@ generic map (
 port map (
     clk_i           => clk_i,
     reset_i         => reset_i,
+    ENCODING        => "00",
     enable_i        => crc_enable_i,
     clock_i         => biss_sck_rising_edge,
     data_i          => biss_dat_i,