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Merge pull request #142 from PandABlocks/encoders_tidy
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Tidy-up of encoders and slow interface
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@tomtrafford
tomtrafford authored Sep 20, 2023
2 parents 8ed6881 + c98aa49 commit 5e7d834
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176 changes: 93 additions & 83 deletions common/hdl/encoders/encoders.vhd
View file
Original file line number Diff line number Diff line change
Expand Up @@ -126,30 +126,34 @@ signal Z_OUT : std_logic;
signal DATA_OUT : std_logic;

signal CLK_OUT : std_logic;

signal CLK_IN : std_logic;

signal Bs0_t : std_logic;
signal OUTENC_PROTOCOL : std_logic_vector(2 downto 0);
signal OUTENC_PROTOCOL_rb : std_logic_vector(2 downto 0);
signal INENC_PROTOCOL_rb : std_logic_vector(2 downto 0);

begin

-- Unused Nets.
inenc_dir <= '0';
inenc_dir <= '1';
outenc_dir <= '0';
Am0_opad <= '0';
Zm0_opad <= '0';

-----------------------------OUTENC---------------------------------------------
--------------------------------------------------------------------------------
-- When using the monitor control card, only the B signal is used as this is
-- used to generate the Clock inputted to the Inenc.


-- When using the Monitor Daughter Card, only the Input Ecoder protocol is used
OUTENC_PROTOCOL <=
INENC_PROTOCOL_i when DCARD_MODE_i(3 downto 1) = DCARD_MONITOR
else OUTENC_PROTOCOL_i;

-- Assign outputs
A_OUT <= a_ext_i when (OUTENC_PROTOCOL_i = c_ABZ_PASSTHROUGH) else quad_a;
B_OUT <= b_ext_i when (OUTENC_PROTOCOL_i = c_ABZ_PASSTHROUGH) else quad_b;
Z_OUT <= z_ext_i when (OUTENC_PROTOCOL_i = c_ABZ_PASSTHROUGH) else '0';
DATA_OUT <= data_ext_i when (OUTENC_PROTOCOL_i = c_DATA_PASSTHROUGH) else
bdat when (OUTENC_PROTOCOL_i = c_BISS) else sdat;
A_OUT <= a_ext_i when (OUTENC_PROTOCOL = c_ABZ_PASSTHROUGH) else quad_a;
B_OUT <= b_ext_i when (OUTENC_PROTOCOL = c_ABZ_PASSTHROUGH) else quad_b;
Z_OUT <= z_ext_i when (OUTENC_PROTOCOL = c_ABZ_PASSTHROUGH) else '0';
DATA_OUT <= data_ext_i when (OUTENC_PROTOCOL = c_DATA_PASSTHROUGH) else
bdat when (OUTENC_PROTOCOL = c_BISS) else sdat;

--
-- INCREMENTAL OUT
Expand Down Expand Up @@ -203,26 +207,30 @@ port map (
--
-- Link status information is valid only for loopback configuration
--------------------------------------------------------------------------

OUTENC_PROTOCOL_rb <= DCARD_MODE_i(18 downto 16);

process(clk_i)
begin
if rising_edge(clk_i) then
case (OUTENC_PROTOCOL_i) is
when "000" => -- INC
OUTENC_HEALTH_o <= (others=>'0');

when "001" => -- SSI & Loopback
OUTENC_HEALTH_o <= (others=>'0');

when "010" => -- BISS & Loopback
OUTENC_HEALTH_o <= health_biss_slave;

when c_enDat => -- enDat
OUTENC_HEALTH_o <= std_logic_vector(to_unsigned(2,32)); --ENDAT not implemented

when others =>
OUTENC_HEALTH_o <= (others=>'0');

end case;
if DCARD_MODE_i(3 downto 1) = DCARD_MONITOR then
OUTENC_HEALTH_o <= std_logic_vector(to_unsigned(3,32));
elsif OUTENC_PROTOCOL_rb /= OUTENC_PROTOCOL then
OUTENC_HEALTH_o <= std_logic_vector(to_unsigned(4,32));
else
case (OUTENC_PROTOCOL) is
when "000" => -- INC
OUTENC_HEALTH_o <= (others=>'0');
when "001" => -- SSI & Loopback
OUTENC_HEALTH_o <= (others=>'0');
when "010" => -- BISS & Loopback
OUTENC_HEALTH_o <= health_biss_slave;
when c_enDat => -- enDat
OUTENC_HEALTH_o <= std_logic_vector(to_unsigned(2,32)); --ENDAT not implemented
when others =>
OUTENC_HEALTH_o <= (others=>'0');
end case;
end if;
end if;
end process;

Expand Down Expand Up @@ -356,51 +364,58 @@ port map (
--
-- Link status information is valid only for loopback configuration
--------------------------------------------------------------------------

INENC_PROTOCOL_rb <= DCARD_MODE_i(10 downto 8);

process(clk_i)
begin
if rising_edge(clk_i) then
case (INENC_PROTOCOL_i) is
when "000" => -- INC
posn <= posn_incr;
STATUS_o(0) <= linkup_incr;
INENC_HEALTH_o(0) <= not(linkup_incr);
INENC_HEALTH_o(31 downto 1)<= (others=>'0');
HOMED_o <= homed_qdec;

when "001" => -- SSI & Loopback
if (DCARD_MODE_i(3 downto 1) = DCARD_MONITOR) then
posn <= posn_ssi_sniffer;
STATUS_o(0) <= linkup_ssi;
if (linkup_ssi = '0') then
INENC_HEALTH_o <= TO_SVECTOR(2,32);
else
INENC_HEALTH_o <= (others => '0');
if INENC_PROTOCOL_rb /= INENC_PROTOCOL_i then
INENC_HEALTH_o <= TO_SVECTOR(6,32);
else
case (INENC_PROTOCOL_i) is
when "000" => -- INC
posn <= posn_incr;
STATUS_o(0) <= linkup_incr;
INENC_HEALTH_o(0) <= not(linkup_incr);
INENC_HEALTH_o(31 downto 1)<= (others=>'0');
HOMED_o <= homed_qdec;

when "001" => -- SSI & Loopback
if (DCARD_MODE_i(3 downto 1) = DCARD_MONITOR) then
posn <= posn_ssi_sniffer;
STATUS_o(0) <= linkup_ssi;
if (linkup_ssi = '0') then
INENC_HEALTH_o <= TO_SVECTOR(2,32);
else
INENC_HEALTH_o <= (others => '0');
end if;
else -- DCARD_CONTROL
posn <= posn_ssi;
STATUS_o <= (others => '0');
INENC_HEALTH_o <= (others=>'0');
end if;
HOMED_o <= TO_SVECTOR(1,32);

when "010" => -- BISS & Loopback
if (DCARD_MODE_i(3 downto 1) = DCARD_MONITOR) then
posn <= posn_biss_sniffer;
STATUS_o(0) <= linkup_biss_sniffer;
INENC_HEALTH_o <= health_biss_sniffer;
else -- DCARD_CONTROL
posn <= posn_biss;
STATUS_o(0) <= linkup_biss_master;
INENC_HEALTH_o<=health_biss_master;
end if;
else -- DCARD_CONTROL
posn <= posn_ssi;
HOMED_o <= TO_SVECTOR(1,32);

when others =>
INENC_HEALTH_o <= TO_SVECTOR(5,32);
posn <= (others => '0');
STATUS_o <= (others => '0');
INENC_HEALTH_o <= (others=>'0');
end if;
HOMED_o <= TO_SVECTOR(1,32);

when "010" => -- BISS & Loopback
if (DCARD_MODE_i(3 downto 1) = DCARD_MONITOR) then
posn <= posn_biss_sniffer;
STATUS_o(0) <= linkup_biss_sniffer;
INENC_HEALTH_o <= health_biss_sniffer;
else -- DCARD_CONTROL
posn <= posn_biss;
STATUS_o(0) <= linkup_biss_master;
INENC_HEALTH_o<=health_biss_master;
end if;
HOMED_o <= TO_SVECTOR(1,32);

when others =>
INENC_HEALTH_o <= TO_SVECTOR(5,32);
posn <= (others => '0');
STATUS_o <= (others => '0');
HOMED_o <= TO_SVECTOR(1,32);
end case;
HOMED_o <= TO_SVECTOR(1,32);
end case;
end if;
end if;
end process;

Expand All @@ -416,9 +431,9 @@ begin
when "000" => -- INC
inenc_ctrl <= "111";
when "001" => -- SSI
inenc_ctrl <= "101";
inenc_ctrl <= "100";
when "010" => -- BiSS-C
inenc_ctrl <= "101";
inenc_ctrl <= inenc_dir & "00";
when "011" => -- EnDat
inenc_ctrl <= inenc_dir & "00";
when others =>
Expand Down Expand Up @@ -454,6 +469,7 @@ IOBUF_Zm0 : entity work.iobuf_registered port map (
);

Bm0_opad <= CLK_OUT;
Zm0_opad <= not inenc_dir;

a_filt : entity work.delay_filter port map(
clk_i => clk_i,
Expand Down Expand Up @@ -492,21 +508,19 @@ begin
if (reset_i = '1') then
outenc_ctrl <= "000";
else
case (OUTENC_PROTOCOL_i) is
case (OUTENC_PROTOCOL) is
when "000" => -- INC
outenc_ctrl <= "000";
when "001" => -- SSI
outenc_ctrl <= "011";
outenc_ctrl <= "010";
when "010" => -- BiSS
outenc_ctrl <= outenc_dir & "10";
when "011" => -- EnDat
outenc_ctrl <= outenc_dir & "10";
-- when "100" => -- Pass-Through
-- outenc_ctrl <= "000";
when "101" =>
outenc_ctrl <= "011"; -- DATA PassThrough
outenc_ctrl <= "010"; -- DATA PassThrough
when others =>
outenc_ctrl <= "000";
outenc_ctrl <= "000"; -- ABZ Passthrough
end case;
end if;
end if;
Expand All @@ -520,15 +534,11 @@ IOBUF_As0 : entity work.iobuf_registered port map (
IO => As0_pad_io
);

-- When using a Monitor card the B signal will need to be enabled, for using the CLK
-- regardless of the protocol.
Bs0_T <= '1' when (DCARD_MODE_i(3 downto 1) = DCARD_MONITOR) else outenc_ctrl(1);

IOBUF_Bs0 : entity work.iobuf_registered port map (
clock => clk_i,
I => Bs0_opad,
O => Bs0_ipad,
T => Bs0_T,
T => outenc_ctrl(1),
IO => Bs0_pad_io
);

Expand All @@ -541,9 +551,9 @@ IOBUF_Zs0 : entity work.iobuf_registered port map (
);

-- A output is shared between incremental and absolute data lines.
As0_opad <= A_OUT when (OUTENC_PROTOCOL_i(1 downto 0) = "00") else DATA_OUT;
As0_opad <= A_OUT when (OUTENC_PROTOCOL(1 downto 0) = "00") else DATA_OUT;
Bs0_opad <= B_OUT;
Zs0_opad <= Z_OUT;
Zs0_opad <= Z_OUT when (OUTENC_PROTOCOL(1 downto 0) = "00") else not outenc_dir;

INENC_A_o <= A_IN;
INENC_B_o <= B_IN;
Expand Down
1 change: 1 addition & 0 deletions modules/inenc/inenc.block.ini
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Original file line number Diff line number Diff line change
Expand Up @@ -89,6 +89,7 @@ description: Table status
3: CRC error (for BISS)
4: Error bit active (for BISS)
5: ENDAT not implemented
6: Protocol readback error

[VAL]
type: pos_out
Expand Down
2 changes: 2 additions & 0 deletions modules/outenc/outenc.block.ini
View file
Original file line number Diff line number Diff line change
Expand Up @@ -68,6 +68,8 @@ description: Table status
0: OK
1: Biss timeout error (did not received right number of sck for biss frame)
2: ENDAT not implemented
3: OUTENC unused (MONITOR mode)
4: Protocol readback error

[DCARD_TYPE]
type: read enum
Expand Down
13 changes: 4 additions & 9 deletions modules/system/hdl/system_registers.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -26,7 +26,6 @@ entity system_registers is
port (
clk_i : in std_logic;
reset_i : in std_logic;
DCARD_MODE_i : in std32_array(ENC_NUM-1 downto 0);
OUTENC_PROT_i : in std32_array(ENC_NUM-1 downto 0);
OUTENC_PROT_WSTB_i : in std_logic_vector(ENC_NUM-1 downto 0);
INENC_PROT_i : in std32_array(ENC_NUM-1 downto 0);
Expand Down Expand Up @@ -84,8 +83,6 @@ begin
slow_tlp_o.address <= (others => '0');
slow_tlp_o.data <= (others => '0');
else
-- Single clock cycle strobe
slow_tlp_o.strobe <= '0';
-- INENC PROTOCOL Slow Registers
if (or_reduce(INENC_PROT_WSTB_i) = '1') then
inenc_ind := ONEHOT_INDEX(INENC_PROT_WSTB_i);
Expand All @@ -96,22 +93,20 @@ begin
elsif (or_reduce(OUTENC_PROT_WSTB_i) = '1') then
outenc_ind := ONEHOT_INDEX(OUTENC_PROT_WSTB_i);
slow_tlp_o.strobe <= '1';
-- When using a monitor card, the protocol needs to make sure the CLK is enabled.
if (DCARD_MODE_i(outenc_ind)(3 downto 1) = DCARD_MONITOR) then
slow_tlp_o.data <= x"0000000" & '0' & OUTENC_PROT_i(outenc_ind)(2) & '1' & OUTENC_PROT_i(outenc_ind)(0);
else
slow_tlp_o.data <= OUTENC_PROT_i(outenc_ind);
end if;
slow_tlp_o.data <= OUTENC_PROT_i(outenc_ind);
slow_tlp_o.address <= OUTPROT_ADDR_LIST(outenc_ind);
-- TTLIN TERM Slow Registers
elsif (or_reduce(TTLIN_TERM_WSTB_i) = '1') then
ttlin_ind := ONEHOT_INDEX(TTLIN_TERM_WSTB_i);
slow_tlp_o.strobe <= '1';
slow_tlp_o.data <= TTLIN_TERM_i(ttlin_ind);
slow_tlp_o.address <= TTLTERM_ADDR_LIST(ttlin_ind);
else
slow_tlp_o.strobe <= '0';
end if;
end if;
end if;
end process;

end rtl;

1 change: 0 additions & 1 deletion modules/system/hdl/system_top.vhd
View file
Original file line number Diff line number Diff line change
Expand Up @@ -120,7 +120,6 @@ system_registers : entity work.system_registers
port map (
clk_i => clk_i,
reset_i => reset_i,
DCARD_MODE_i => DCARD_MODE,
OUTENC_PROT_i => OUTENC_PROT_i,
OUTENC_PROT_WSTB_i => OUTENC_PROT_WSTB_i,
INENC_PROT_i => INENC_PROT_i,
Expand Down

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