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Digital logic design tool and simulator

Java 5,160 665 Updated Jan 7, 2025

GPT4All: Run Local LLMs on Any Device. Open-source and available for commercial use.

C++ 71,792 7,803 Updated Jan 17, 2025

Verilator open-source SystemVerilog simulator and lint system

C++ 2,673 628 Updated Jan 18, 2025

GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard Verilog VCD/EVCD files and allows their viewing.

C 688 123 Updated Jan 17, 2025

The official git repository for Contiki, the open source OS for the Internet of Things

C 3,731 2,575 Updated Apr 6, 2024

The OpenRISC 1000 architectural simulator

C 72 43 Updated Aug 26, 2024

Spike, a RISC-V ISA Simulator

C 2,540 885 Updated Jan 18, 2025

Official QEMU mirror. Please see https://www.qemu.org/contribute/ for how to submit changes to QEMU. Pull Requests are ignored. Please only use release tarballs from the QEMU website.

C 10,757 5,710 Updated Jan 19, 2025

Buildroot, making embedded Linux easy. Note that this is not the official repository, but only a mirror. The official Git repository is at https://gitlab.com/buildroot.org/buildroot/. Do not open i…

Makefile 2,845 2,459 Updated Jan 19, 2025

OpenEmbedded/Yocto layer for RISC-V Architecture

BitBake 373 144 Updated Jan 15, 2025

Qiskit is an open-source SDK for working with quantum computers at the level of extended quantum circuits, operators, and primitives.

Python 5,539 2,421 Updated Jan 19, 2025

Magic VLSI Layout Tool

C 505 108 Updated Jan 16, 2025

Project Website: https://inkscape.org - Code Repository: https://gitlab.com/inkscape/inkscape - Draw freely. 🖌

2,334 188 Updated Mar 3, 2022

Algorithm to hardware compilation tools (e.g. C to VHDL).

VHDL 39 16 Updated Jan 10, 2025

Multi-platform nightly builds of open source digital design and verification tools

Shell 925 85 Updated Jan 20, 2025

VUnit is a unit testing framework for VHDL/SystemVerilog

VHDL 756 268 Updated Jan 19, 2025

Official doxygen git repository

C++ 5,806 1,289 Updated Jan 19, 2025

Flexible and powerful data analysis / manipulation library for Python, providing labeled data structures similar to R data.frame objects, statistical functions, and much more

Python 44,346 18,142 Updated Jan 17, 2025

Verilog library for ASIC and FPGA designers

Verilog 1,236 290 Updated May 8, 2024

SonicBOOM: The Berkeley Out-of-Order Machine

Scala 1,786 428 Updated Oct 1, 2024

The MyHDL development repository

Python 1,059 250 Updated Jan 15, 2025

This is an active mirror of the KiCad development branch, which is hosted at GitLab (updated every time something is pushed). Pull requests on GitHub are not accepted or watched.

C++ 2,013 491 Updated Jan 20, 2025
SystemVerilog 81 17 Updated Sep 20, 2023

SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows

Python 419 78 Updated Dec 11, 2024

🌊 Digital timing diagram rendering engine

JavaScript 3,044 373 Updated Apr 2, 2024

Open source O-RAN 5G CU/DU solution from Software Radio Systems (SRS) https://docs.srsran.com/projects/project

C++ 656 202 Updated Jan 17, 2025

UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improv…

VHDL 383 96 Updated Jan 19, 2025

OpenSCAD - The Programmers Solid 3D CAD Modeller

C++ 7,330 1,243 Updated Jan 20, 2025

VHDL synthesis (based on ghdl)

VHDL 316 33 Updated Dec 27, 2024

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

SystemVerilog 888 284 Updated Nov 15, 2024
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