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fix(Rename): remove the handling of dest being src in bypassCond #3752

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fix(Rename): remove the handling of dest being src in bypassCond #3752

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2 changes: 1 addition & 1 deletion coupledL2
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Submodule coupledL2 updated 6 files
+29 −71 src/main/scala/coupledL2/tl2chi/MSHR.scala
+1 −4 src/main/scala/coupledL2/tl2chi/TXDAT.scala
+0 −3 src/main/scala/coupledL2/tl2chi/TXREQ.scala
+1 −4 src/main/scala/coupledL2/tl2chi/TXRSP.scala
+0 −134 src/main/scala/coupledL2/tl2chi/chi/Message.scala
+2 −6 src/test/scala/chi/TestTop.scala
2 changes: 1 addition & 1 deletion ready-to-run
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Submodule ready-to-run updated 2 files
+ − riscv64-nemu-interpreter-dual-so
+ − riscv64-nemu-interpreter-so
14 changes: 7 additions & 7 deletions src/main/scala/xiangshan/backend/rename/Rename.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -491,23 +491,23 @@ class Rename(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHe
io.out(0).bits.pdest := Mux(isMove(0), uops(0).psrc.head, uops(0).pdest)

// psrc(n) + pdest(1)
val bypassCond: Vec[MixedVec[UInt]] = Wire(Vec(numRegSrc + 1, MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W)))))
val bypassCond: Vec[MixedVec[UInt]] = Wire(Vec(numRegSrc, MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W)))))
require(io.in(0).bits.srcType.size == io.in(0).bits.numSrc)
private val pdestLoc = io.in.head.bits.srcType.size // 2 vector src: v0, vl&vtype
println(s"[Rename] idx of pdest in bypassCond $pdestLoc")
for (i <- 1 until RenameWidth) {
val v0Cond = io.in(i).bits.srcType.zipWithIndex.map{ case (s, i) =>
if (i == 3) (s === SrcType.vp) || (s === SrcType.v0)
else false.B
} :+ needV0Dest(i)
}
val vlCond = io.in(i).bits.srcType.zipWithIndex.map{ case (s, i) =>
if (i == 4) s === SrcType.vp
else false.B
} :+ needVlDest(i)
val vecCond = io.in(i).bits.srcType.map(_ === SrcType.vp) :+ needVecDest(i)
val fpCond = io.in(i).bits.srcType.map(_ === SrcType.fp) :+ needFpDest(i)
val intCond = io.in(i).bits.srcType.map(_ === SrcType.xp) :+ needIntDest(i)
val target = io.in(i).bits.lsrc :+ io.in(i).bits.ldest
}
val vecCond = io.in(i).bits.srcType.map(_ === SrcType.vp)
val fpCond = io.in(i).bits.srcType.map(_ === SrcType.fp)
val intCond = io.in(i).bits.srcType.map(_ === SrcType.xp)
val target = io.in(i).bits.lsrc
for ((((((cond1, (condV0, condVl)), cond2), cond3), t), j) <- vecCond.zip(v0Cond.zip(vlCond)).zip(fpCond).zip(intCond).zip(target).zipWithIndex) {
val destToSrc = io.in.take(i).zipWithIndex.map { case (in, j) =>
val indexMatch = in.bits.ldest === t
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