Skip to content

Commit

Permalink
SRAM: use the clock gating cell from utility (#175)
Browse files Browse the repository at this point in the history
  • Loading branch information
xiaokamikami authored Apr 22, 2024
1 parent 4c00249 commit 33d2ece
Show file tree
Hide file tree
Showing 4 changed files with 5 additions and 57 deletions.
34 changes: 0 additions & 34 deletions src/main/resources/STD_CLKGT_func.v

This file was deleted.

8 changes: 2 additions & 6 deletions src/main/scala/huancun/BaseDirectory.scala
Original file line number Diff line number Diff line change
Expand Up @@ -26,7 +26,7 @@ import chisel3.util.random.LFSR
import freechips.rocketchip.tilelink.TLMessages
import freechips.rocketchip.util.{Pow2ClockDivider, ReplacementPolicy}
import huancun.utils._
import utility.{Code}
import utility.{ClockGate, Code}

trait BaseDirResult extends HuanCunBundle {
val idOH = UInt(mshrsAll.W) // which mshr the result should be sent to
Expand Down Expand Up @@ -106,13 +106,9 @@ class SubDirectory[T <: Data](
val resetIdx = RegInit((sets - 1).U)
val metaArray = Module(new SRAMTemplate(chiselTypeOf(dir_init), sets, ways, singlePort = true, input_clk_div_by_2 = clk_div_by_2))

val clkGate = Module(new STD_CLKGT_func)
val clk_en = RegInit(false.B)
clk_en := ~clk_en
clkGate.io.TE := false.B
clkGate.io.E := clk_en
clkGate.io.CK := clock
val masked_clock = clkGate.io.Q
val masked_clock = ClockGate(false.B, clk_en, clock)

val tag_wen = io.tag_w.valid
val dir_wen = io.dir_w.valid
Expand Down
18 changes: 2 additions & 16 deletions src/main/scala/huancun/utils/SRAMWrapper.scala
Original file line number Diff line number Diff line change
Expand Up @@ -3,17 +3,7 @@ package huancun.utils
import chisel3._
import chisel3.util._
import freechips.rocketchip.util.Pow2ClockDivider

class STD_CLKGT_func extends BlackBox with HasBlackBoxResource {
val io = IO(new Bundle {
val TE = Input(Bool())
val E = Input(Bool())
val CK = Input(Clock())
val Q = Output(Clock())
})

addResource("/STD_CLKGT_func.v")
}
import utility.ClockGate

class SRAMWrapper[T <: Data]
(
Expand Down Expand Up @@ -41,13 +31,9 @@ class SRAMWrapper[T <: Data]
gen, innerSet, 1, singlePort = true, input_clk_div_by_2 = clk_div_by_2
))

val clkGate = Module(new STD_CLKGT_func)
val clk_en = RegInit(false.B)
clk_en := ~clk_en
clkGate.io.TE := false.B
clkGate.io.E := clk_en
clkGate.io.CK := clock
val masked_clock = clkGate.io.Q
val masked_clock = ClockGate(false.B, clk_en, clock)

if (clk_div_by_2) {
sram.clock := masked_clock
Expand Down

0 comments on commit 33d2ece

Please sign in to comment.