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FIX: bufIdx width should increase after #SinkCbufBlocks increase (#174)
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or sinkC bufferVals will be mistakenly cleared, causing system stall
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Ivyfeather authored Apr 19, 2024
1 parent a69ea2c commit 4c00249
Showing 1 changed file with 1 addition and 1 deletion.
2 changes: 1 addition & 1 deletion src/main/scala/huancun/HuanCun.scala
Original file line number Diff line number Diff line change
Expand Up @@ -67,9 +67,9 @@ trait HasHuanCunParameters {
else cacheParams.clientCaches.head.aliasBitsOpt

val bufBlocks = mshrs / 2
val bufIdxBits = log2Ceil(bufBlocks)
val sinkCbufBlocks = mshrsAll // sinkC buffer require more blocks to avoid deadlock
require(sinkCbufBlocks >= bufBlocks, "sinkCbufBlocks should bigger than bufBlocks")
val bufIdxBits = log2Ceil(mshrsAll) // should be MAX{bufBlocks, sinkCBufBlocks}

val alwaysReleaseData = cacheParams.alwaysReleaseData

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