Rebase rvh squash 0912 #171

jueshiwenli · 2024-09-12T13:19:00Z

No description provided.

Change-Id: I26add7336e515658b0bbdaebeb00bb2848826715

Change-Id: I5369768610a052299a3351b31677969d6a5d2f90

- add mcountinhibit - add mhpmcounter - update mcounteren config - add menvcfg

Change-Id: I6fe28f5654b5312eb7a3d77013f6f99fd006fa93

Change-Id: Ibffd33bff95044db9ec4f7e28c2c60ff874a0bb8

Change-Id: Ib4b056c41e166ac374077b26567b31e9b681cfc6

Change-Id: I88ccd869c7b33d64aef57d3e84fdc8e947d1c770

Change-Id: I88f5910c6da05630eebd05cfcbe51ccffb376c92

In h-checkpoint ,we don't need to designate gcpt-restore Change-Id: I3433139c7e6b7f2774f3d9a1f7f0a5dbb874ea9e

make pmp read with different mask Change-Id: If82e1f518e32c6e7da78d39664c124773930e9e8

- add hstatus - fix bug of vsstatus - add h difftest - add hie - open virtualization mode - fix bugs of mstatus & vir mode - fix bugs of mastatus mask - fix bugs of hstatus & virt mode - fix bugs of write h csr

- when cpu.v =1 sret need update vsstatus - else need update v & hstatus Change-Id: Ie7af67adae3c2fe337306517d0bec99ac4587056

- when in s mode judge whether is in hs - when in hs,update vsstatus v vscause vsepc Change-Id: I49f790f565fba928c751590084420b24f3a1caff

- fix bugs of write vsscratch - fix bugs of pc state Change-Id: I692366a494d2aeaff0e7f56035a6440e51ea550a

when need translate tlb will check translate mode two stage translate mode : - VSstage - Gstage Change-Id: I18a70651bf1a89a821609b417940fea5e5559bf7

Change-Id: Idf45d80dde0450227a087ee14b1f2fa0680e3787

- use g_trap update htval/mtval2 only g-stage - when vmode need to update vsstatus instead of sstatus - when write sstatus ,sometimes need to update vsstatus Change-Id: I33edbb6ab81a82f65267878447e64e27b4e3a24a

Change-Id: I1baf3d38986371b3319cb3524d066c81929fe07b

Change-Id: I919f19814fe3ecf58de7ca551264dcdadc1d6bdc

when fault in vsstage need to endwalk and return fix wrong of paddr Change-Id: I707f14fb8ab57416dd6fb49d6c799ba70580fa24

- fix bugs of write vsstatus - fix bugs of satp & hie & sie - fix bugs of hcountern - fix bugs of hip & hvip Change-Id: I16e0bb4bec13c66b7ab814d2522db1009451dfdc

- when vsatp mode = 0 gstage need change translate level - add misalign data addr check Change-Id: Iabafd8726e8623f8ae0347f58490a43d7a879b29

- support h-csr update - fix bugs of status vmode=1 - fix bugs of sepc stval scause Change-Id: Id56a083364550f1165c4f4f2413cf7b6c491ee3c

Change-Id: I6347d4ffd8dfca2c54b92e0573cf63dd0480367f

- when v = 1 , npc = vsepc - initstate need set virt - update pte.a & pte.d by pagefault

- fix bugs of update vsstatus - fix bugs of update mstatus - rvh wfi need check hvfault - fix bugs of update mstatus - fix bugs of stvec satp stvec - fix bugs of scountern - fix bugs of read sie Change-Id: I8e4d339eebf1bf80c2fe5337a9d9f4abbcc54262

- hgatp.mode == 8 || vsatp.mode == 8 need translate - judge address before start g_ptw - vsatpmode0, gpaddr == vaddr - when coalesce, need to return different gpaddr Change-Id: Ic8210e97a689e47bd457fc4cc2638550694f33b4

Change-Id: I3b0f7858d4a27a23533628a3c38c50f41b5e9305

Change-Id: If3b3d3af7df6d460c7e6e106f87f5348927ab3d3

- all stage entry need put highest level in vs & g stage - fix bugs of vsatp0mode gpaddr - fix bugs of hit in l1tln gstage gPaddr - allstsge hit need to check vsPte - hfence.gvma will flush tlb with addr & hgatp - hfence.vvma will flush tlb with addr & vsatp Change-Id: I341eb4c17497c41660352e51cae57c0294e26f6b

- add h-difftest when pagefault - add stats of pagefault times Change-Id: I51bcd1ebf3d0e7eda91ab335e775e829ec030382

Change-Id: Ifdd38b47f6222c1ab6e285f46644b837dc80eb39

- support hfence - when hit in h-l2tlb the result will be send after set cycle - check tlb before ptw send request

Change-Id: Ibf39612734e9ec64bfef3231c4732989a910ff9c

Change-Id: I842f48f4c78bd1f1b4dbe7b591a466beb924e167

shinezyy · 2024-09-13T06:09:13Z

src/arch/riscv/regs/misc.hh

@@ -851,7 +851,8 @@ const RegVal MSTATUS_MASK = STATUS_SD_MASK | STATUS_SXL_MASK |
                            STATUS_SPP_MASK | STATUS_MPIE_MASK |
                            STATUS_SPIE_MASK | STATUS_UPIE_MASK |
                            STATUS_MIE_MASK | STATUS_SIE_MASK |
-                            STATUS_UIE_MASK;


Delete old code?

shinezyy · 2024-09-13T06:12:07Z

src/arch/riscv/isa/formats/standard.isa

@@ -345,7 +345,8 @@ def template CSRExecute {{
        RegVal data, olddata;
        auto lowestAllowedMode = (PrivilegeMode)bits(csr, 9, 8);
        auto pm = (PrivilegeMode)xc->readMiscReg(MISCREG_PRV);
-        if (pm < lowestAllowedMode) {
+        if ((pm < lowestAllowedMode)&&
+            ((csr <CSR_HSTATUS) ||(csr >CSR_HGATP)) && ((csr <CSR_VSSTATUS) ||(csr > CSR_VSATP))) {


format thiese two line of code?

csr <CSR_HSTATUS --> csr < CSR_HSTATUS
) ||( --> ) || (

shinezyy · 2024-09-13T06:13:36Z

src/cpu/base.cc

+            diffAllStates->gem5RegFile.vsscratch = gem5_val;
+            if (!diff_at)
+                diff_at = ValueDiff;
+        }


Can we rewrite this chunk of code with a function, a template function, or a macro?

It looks too redundant

shinezyy · 2024-09-13T06:14:08Z

src/cpu/base.hh

@@ -743,7 +743,7 @@ class BaseCPU : public ClockedObject
        uint64_t amoOldGoldenValue;
        // Register address causing difftest error
        bool errorRegsValue[96];// 32 regs + 32fprs +32 vprs
-        bool errorCsrsValue[32];// CsrRegIndex
+        bool errorCsrsValue[36];// CsrRegIndex


Can we use a enum or macro here?

shinezyy · 2024-09-13T06:14:48Z

src/arch/riscv/isa/decoder.isa

-                                status.spp = PRV_U;
-                                xc->setMiscReg(MISCREG_STATUS, status);
-                                NPC = xc->readMiscReg(MISCREG_SEPC);
+                            bool writeSign = false;


local_variable should use snake_case

shinezyy · 2024-09-13T06:15:33Z

src/arch/riscv/faults.cc

+            if (pp != PRV_M && (tc->readMiscReg(MISCREG_VIRMODE) == 1) &&
+                bits(tc->readMiscReg(MISCREG_HEDELEG), _code) != 0) {
+                prvh = PRV_HS;
+            }


the if block and else block seems to be the same?

redundancy has not resolved yet @jueshiwenli ?

shinezyy · 2024-09-13T09:38:52Z

src/arch/riscv/pagetable_walker.cc

+        if ((translateMode == twoStageMode) && (inGstage)){
+            mainFault = twoStageStepWalk(write);
+        }
+        else if ((translateMode == twoStageMode) && (!inGstage)){


} else if {

shinezyy · 2024-09-13T09:38:56Z

src/arch/riscv/pagetable_walker.cc

+        else if ((translateMode == twoStageMode) && (!inGstage)){
+            mainFault = twoStageWalk(write);
+        }
+        else{


} else if {

shinezyy · 2024-09-13T09:40:19Z

src/arch/riscv/tlb.cc

+            code = ExceptionCode::STORE_PAGE;
+        else
+            code = ExceptionCode::INST_PAGE;
+    }


Are if block and else block the same?

not resolved yet @jueshiwenli

shinezyy · 2024-09-13T09:41:04Z

src/arch/riscv/tlb.cc

+    }
+    if (virt != 0) {
+        if (vsatp.mode == 0)
+            assert(0);


assert (vsatp.mode != 0);

shinezyy · 2024-09-13T09:41:42Z

src/arch/riscv/tlb.cc

+        if (vsatp.mode == 0)
+            assert(0);
+    } else {
+        assert(0);


asssert (virt != 0);

shinezyy · 2024-09-13T10:00:23Z

src/arch/riscv/tlb.cc

+                        lookupL2TLB(vpn + step * i, entry.vmid, BaseMMU::Read, true, choose, false, translateMode);
+                else
+                    newEntry =
+                        lookupL2TLB(vpn + step * i, entry.asid, BaseMMU::Read, true, choose, false, translateMode);


shinezyy · 2024-09-13T10:01:33Z

src/arch/riscv/tlb.cc

+            for (i = 0; i < l2TlbSpSize * l2tlbLineSize; i = i + l2tlbLineSize) {
+                if (tlbL2Sp[i].trieHandle)
+                    l2TLBRemove(i, L_L2sp1);
+            }


There should be a function, and call this function 4 times

shinezyy · 2024-09-13T10:01:46Z

src/arch/riscv/tlb.cc

+            for (i = 0; i < l2TlbSpSize * l2tlbLineSize; i = i + l2tlbLineSize) {
+                if (tlbL2Sp[i].trieHandle)
+                    l2TLBRemove(i, L_L2sp1);
+            }


There should be a function, and call this function 4 times

shinezyy · 2024-09-13T10:02:34Z

src/arch/riscv/tlb.cc

+                    l2TLBRemove(i, L_L2L3);
+                    DPRINTF(TLBVerbose3, "l2l3 remove vaddr %#x vpn %#x vpnl2l3\n", tlbL2L3[i].vaddr, vpn, vpnl2l3);
+                }
+            }
        }


There should be a function, and call this function x times.

shinezyy · 2024-09-13T10:03:08Z

src/arch/riscv/tlb.cc

+    if (isStage2)
+        l2tlb = this;
+    else
+        l2tlb = static_cast<TLB *>(nextLevel());


- Only check misalignDataAddr in two stage translate - fix bugs of remove l2tlb

Change-Id: I27cdfd1370d1e702c69cc68ba395f4ef1de82dc8

- default off h csr diff - add switch to enable enabledifftesInstTrace Change-Id: I91433e72310c8311dace7064ae0c0c3f6c71ed34

Change-Id: Ifcb9a9982b93db26e3e37df4332f433452f8e762

- fix bug of difftest, when valuediff need panic - use DiffValue flag enable difftest trace - clean difftest code Change-Id: Ie5409ea04a892d7f7a878345db37df482d2e68f1

shinezyy and others added 30 commits September 12, 2024 21:02

arch-riscv: add RISCV-H extension CSRs, WIP

50c8b54

arch-riscv: set misa with H-ext

f1c8080

Change-Id: I26add7336e515658b0bbdaebeb00bb2848826715

arch-riscv: fix bug of pmp

eca7e53

Change-Id: I5369768610a052299a3351b31677969d6a5d2f90

arch-riscv: add mhpm & menvcfg & fix bugs

a53407c

- add mcountinhibit - add mhpmcounter - update mcounteren config - add menvcfg

dev: Add nemu plic

7d2c626

Change-Id: I6fe28f5654b5312eb7a3d77013f6f99fd006fa93

arch-riscv: make mideleg adapt h-ext

01e50ac

Change-Id: Ibffd33bff95044db9ec4f7e28c2c60ff874a0bb8

arch-riscv: add hfence.gvma

3f69822

Change-Id: Ib4b056c41e166ac374077b26567b31e9b681cfc6

arch-riscv: make satp only adapt sv39

6e9249d

Change-Id: I88ccd869c7b33d64aef57d3e84fdc8e947d1c770

dev: add plic read

13eb0a4

Change-Id: I88f5910c6da05630eebd05cfcbe51ccffb376c92

sim: change gcpt-restore config

d45d44c

In h-checkpoint ,we don't need to designate gcpt-restore Change-Id: I3433139c7e6b7f2774f3d9a1f7f0a5dbb874ea9e

arch-riscv: update mstatus mask & mie mask

45afa75

arch-riscv: fix pmp bugs

cc2f259

make pmp read with different mask Change-Id: If82e1f518e32c6e7da78d39664c124773930e9e8

arch-riscv: add & fix bugs of h-csr & add h-diff

caac467

- add hstatus - fix bug of vsstatus - add h difftest - add hie - open virtualization mode - fix bugs of mstatus & vir mode - fix bugs of mastatus mask - fix bugs of hstatus & virt mode - fix bugs of write h csr

arch-riscv: fix bugs of sret

7449394

- when cpu.v =1 sret need update vsstatus - else need update v & hstatus Change-Id: Ie7af67adae3c2fe337306517d0bec99ac4587056

arch-riscv: fix bugs of pf

aa811eb

- when in s mode judge whether is in hs - when in hs,update vsstatus v vscause vsepc Change-Id: I49f790f565fba928c751590084420b24f3a1caff

arch-riscv: fix bugs of hsmode

22ecb45

- fix bugs of write vsscratch - fix bugs of pc state Change-Id: I692366a494d2aeaff0e7f56035a6440e51ea550a

arch-riscv: add two stage translate mode

46d51e2

when need translate tlb will check translate mode two stage translate mode : - VSstage - Gstage Change-Id: I18a70651bf1a89a821609b417940fea5e5559bf7

arch-riscv: add h inst

6180464

Change-Id: Idf45d80dde0450227a087ee14b1f2fa0680e3787

arch-riscv: fix bugs of csr

e847b99

- use g_trap update htval/mtval2 only g-stage - when vmode need to update vsstatus instead of sstatus - when write sstatus ,sometimes need to update vsstatus Change-Id: I33edbb6ab81a82f65267878447e64e27b4e3a24a

arch-riscv: support vmode ecall

e77852f

Change-Id: I1baf3d38986371b3319cb3524d066c81929fe07b

arch-riscv: add ptw tryCoalesce

d3f55e2

Change-Id: I919f19814fe3ecf58de7ca551264dcdadc1d6bdc

arch-riscv: fix bugs of marchid & sstatus

cc76ae7

arch-riscv: fix bugs of two stage ptw

79c4d25

when fault in vsstage need to endwalk and return fix wrong of paddr Change-Id: I707f14fb8ab57416dd6fb49d6c799ba70580fa24

arch-riscv: fix H-csr bugs

55664a7

- fix bugs of write vsstatus - fix bugs of satp & hie & sie - fix bugs of hcountern - fix bugs of hip & hvip Change-Id: I16e0bb4bec13c66b7ab814d2522db1009451dfdc

arch-riscv: Vsatp mode 0 & misalign check

6219ad4

- when vsatp mode = 0 gstage need change translate level - add misalign data addr check Change-Id: Iabafd8726e8623f8ae0347f58490a43d7a879b29

arch-riscv: support h-csr update when fault

8055b35

- support h-csr update - fix bugs of status vmode=1 - fix bugs of sepc stval scause Change-Id: Id56a083364550f1165c4f4f2413cf7b6c491ee3c

cpu: fix bugs of h-difftest

af7202d

Change-Id: I6347d4ffd8dfca2c54b92e0573cf63dd0480367f

arch-riscv: fix bugs of h-ptw & sret

4ad707c

- when v = 1 , npc = vsepc - initstate need set virt - update pte.a & pte.d by pagefault

arch-riscv: fix bugs of h-ptw

78b1080

- hgatp.mode == 8 || vsatp.mode == 8 need translate - judge address before start g_ptw - vsatpmode0, gpaddr == vaddr - when coalesce, need to return different gpaddr Change-Id: Ic8210e97a689e47bd457fc4cc2638550694f33b4

jueshiwenli added 8 commits September 12, 2024 21:15

arch-riscv: add tlb translate mode

60e2d28

Change-Id: I3b0f7858d4a27a23533628a3c38c50f41b5e9305

arch-riscv: add h l1tlb

f334f30

Change-Id: If3b3d3af7df6d460c7e6e106f87f5348927ab3d3

cpu: fix bugs of difftest

80bb38c

- add h-difftest when pagefault - add stats of pagefault times Change-Id: I51bcd1ebf3d0e7eda91ab335e775e829ec030382

arch-riscv: clean h-l1tlb code

efeff16

Change-Id: Ifdd38b47f6222c1ab6e285f46644b837dc80eb39

arch-riscv: add h-l2tlb

02bd763

- support hfence - when hit in h-l2tlb the result will be send after set cycle - check tlb before ptw send request

arch-riscv: fix bugs of pmp

0d58a7e

Change-Id: Ibf39612734e9ec64bfef3231c4732989a910ff9c

arch-riscv: update csr mask

b4f638e

Change-Id: I842f48f4c78bd1f1b4dbe7b591a466beb924e167

jueshiwenli requested review from shinezyy and notlqr September 12, 2024 13:19

notlqr approved these changes Sep 13, 2024

View reviewed changes

shinezyy requested changes Sep 13, 2024

View reviewed changes

jueshiwenli force-pushed the rebase-rvh-squash-0912 branch from bdedf2e to b891f21 Compare September 23, 2024 02:40

jueshiwenli added 6 commits September 27, 2024 16:56

arch-riscv: fix bugs of l2tlb

061c737

- Only check misalignDataAddr in two stage translate - fix bugs of remove l2tlb

arch-riscv: fix bugs of MTINST & MTVAL2

b173f06

Change-Id: I27cdfd1370d1e702c69cc68ba395f4ef1de82dc8

cpu: update difftest display

6b3e019

- default off h csr diff - add switch to enable enabledifftesInstTrace Change-Id: I91433e72310c8311dace7064ae0c0c3f6c71ed34

misc: update ref & restore path

98b7d4f

arch-riscv: clean H-MMU code

d3dd9ef

Change-Id: Ifcb9a9982b93db26e3e37df4332f433452f8e762

cpu: update difftest

7e9b576

- fix bug of difftest, when valuediff need panic - use DiffValue flag enable difftest trace - clean difftest code Change-Id: Ie5409ea04a892d7f7a878345db37df482d2e68f1

jueshiwenli force-pushed the rebase-rvh-squash-0912 branch from b891f21 to 7e9b576 Compare September 27, 2024 09:34

shinezyy approved these changes Oct 8, 2024

View reviewed changes

shinezyy merged commit 546142b into xs-dev Oct 8, 2024
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Rebase rvh squash 0912 #171

Rebase rvh squash 0912 #171

jueshiwenli commented Sep 12, 2024

shinezyy Sep 13, 2024

shinezyy Sep 13, 2024

shinezyy Sep 13, 2024

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shinezyy Sep 13, 2024

shinezyy Sep 25, 2024 •

edited

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Rebase rvh squash 0912 #171

Rebase rvh squash 0912 #171

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jueshiwenli commented Sep 12, 2024

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shinezyy Sep 25, 2024 • edited Loading

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shinezyy Sep 25, 2024 •

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