Merge pull request #171 from OpenXiangShan/rebase-rvh-squash-0912

Merge basic functionality of RVH; Future work: remove redundant code in TLB and PTW

.github/workflows/autotest/gem5.cfg

@@ -15,7 +15,7 @@ log_root = ./log_root
 compile_thread = 70
 #gcpt路径
 gcpt_path = /nfs/home/share/gem5_shared_tools/normal-gcb-restorer.bin
-ref_so_path = /nfs/home/share/gem5_shared_tools/riscv64-nemu-4332a525-so
+ref_so_path = /nfs-nvme/home/share/zhenhao/ref-h/build/riscv64-nemu-interpreter-so
 
 set_var = export NEMU_HOME={ref_so_path}
 

.github/workflows/gem5.yml

@@ -74,7 +74,7 @@ jobs:
         run: CC=gcc CXX=g++ scons build/RISCV/gem5.opt --linker=gold -j64
       - name: XS-GEM5 - Test xiangshan.py simulation scripts
         run: |
-          export GCBV_REF_SO="/nfs/home/share/gem5_shared_tools/riscv64-nemu-4332a525-so"
+          export GCBV_REF_SO="/nfs-nvme/home/share/zhenhao/ref-h/build/riscv64-nemu-interpreter-so"
           export GCB_RESTORER="/nfs/home/share/gem5_shared_tools/normal-gcb-restorer.bin"
           export GEM5_HOME=$(pwd)
           mkdir -p $GEM5_HOME/util/xs_scripts/test
@@ -101,7 +101,7 @@ jobs:
         run: CC=gcc CXX=g++ scons build/RISCV/gem5.opt --linker=gold -j64
       - name: XS-GEM5 - Test xiangshan.py simulation scripts
         run: |
-          export GCBV_REF_SO="/nfs/home/share/gem5_shared_tools/riscv64-nemu-4332a525-so"
+          export GCBV_REF_SO="/nfs-nvme/home/share/zhenhao/ref-h/build/riscv64-nemu-interpreter-so"
           export GCBV_RESTORER="/nfs/home/share/gem5_shared_tools/gcbv-restorer.bin"
           export GEM5_HOME=$(pwd)
           mkdir -p $GEM5_HOME/util/xs_scripts/test_v
@@ -120,7 +120,7 @@ jobs:
           CC=clang CXX=clang++ scons build/RISCV_CHI/gem5.opt -j 48 --gold-linker
       - name: XS-GEM5 - Test xiangshan.py simulation scripts
         run: |
-          export GCBV_MULTI_CORE_REF_SO="/nfs/home/share/gem5_shared_tools/riscv64-dualcore-nemu-4332a525-so"
+          export GCBV_MULTI_CORE_REF_SO="/nfs-nvme/home/share/zhenhao/ref-h/build-multi/riscv64-nemu-interpreter-so"
           export GCB_MULTI_CORE_RESTORER="/nfs/home/share/gem5_shared_tools/gcb-2core-restorer.bin"
           export GEM5_HOME=$(pwd)
           mkdir -p $GEM5_HOME/util/xs_scripts/test_multi_core

configs/common/FSConfig.py

@@ -686,12 +686,16 @@ def makeBareMetalXiangshanSystem(mem_mode, mdesc=None, cmdline=None, np=1, ruby=
     self.mmcs = NemuMMC()
     self.mmcs.pio = self.iobus.mem_side_ports
 
+    self.plic = NemuPlic()
+    self.plic.pio = self.iobus.mem_side_ports
+
     if not ruby:
         self.bridge.ranges = [
             AddrRange(self.uartlite.pio_addr, self.uartlite.pio_addr +
             self.uartlite.pio_size),
             AddrRange(self.lint.pio_addr, self.lint.pio_addr + self.lint.pio_size),
             AddrRange(self.mmcs.pio_addr, self.mmcs.pio_addr + self.mmcs.pio_size),
+            AddrRange(self.plic.pio_addr, self.plic.pio_addr + self.plic.pio_size),
             ]
 
     self.workload.reset_vect = 0x80000000

src/arch/amdgpu/vega/faults.hh

@@ -62,7 +62,7 @@ class VegaFault : public FaultBase
 
     FaultName name() const override { return _name; }
     bool isInterrupt() const { return _interrupt; }
-    ExceptionCode exception() const { return _code; }
+    uint64_t exception() const override{ return _code; }
     virtual RegVal trap_value() const { return 0; }
 
     void invoke(ThreadContext *tc, const StaticInstPtr &inst) override;

src/arch/generic/SConscript

@@ -51,6 +51,8 @@ DebugFlag('PageTableWalker',
           "Page table walker state machine debugging")
 DebugFlag('PageTableWalker2',
           "Page table walker state machine debugging")
+DebugFlag('PageTableWalkerTwoStage',
+          "Page table walker state machine debugging")
 DebugFlag('PageTableWalker3',
           "Page table walker state machine debugging")
 DebugFlag('autoNextline',

src/arch/generic/mmu.hh

@@ -53,7 +53,7 @@ class BaseTLB;
 class BaseMMU : public SimObject
 {
   public:
-    enum Mode { Read, Write, Execute };
+    enum Mode { Read, Write, Execute};
 
     class Translation
     {

src/arch/riscv/faults.cc

@@ -65,7 +65,15 @@ RiscvFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
     if (FullSystem) {
         PrivilegeMode pp = (PrivilegeMode)tc->readMiscReg(MISCREG_PRV);
         PrivilegeMode prv = PRV_M;
+        PrivilegeMode prvh = PRV_M;
         STATUS status = tc->readMiscReg(MISCREG_STATUS);
+        HSTATUS hstatus = tc->readMiscReg(MISCREG_HSTATUS);
+        VSSTATUS vsstatus = tc->readMiscReg(MISCREG_VSSTATUS);
+        auto vmode = tc->readMiscReg(MISCREG_VIRMODE);
+        bool hs_mode_pc = false;
+        if ((_code == ECALL_SUPER)  && vmode){
+            _code = ECALL_VS;
+        }
 
         // According to riscv-privileged-v1.11, if a NMI occurs at the middle
         // of a M-mode trap handler, the state (epc/cause) will be overwritten
@@ -97,8 +105,21 @@ RiscvFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
             }
         }
 
+        if (isInterrupt()) {
+            if (pp != PRV_M && (tc->readMiscReg(MISCREG_VIRMODE) == 1) &&
+                bits(tc->readMiscReg(MISCREG_HIDELEG), _code) != 0) {
+                prvh = PRV_HS;
+            }
+        } else {
+            if (pp != PRV_M && (tc->readMiscReg(MISCREG_VIRMODE) == 1) &&
+                bits(tc->readMiscReg(MISCREG_HEDELEG), _code) != 0) {
+                prvh = PRV_HS;
+            }
+        }
+
         // Set fault registers and status
         MiscRegIndex cause, epc, tvec, tval;
+        int v = status.mprv ? status.mpv : tc->readMiscReg(MISCREG_VIRMODE);
         switch (prv) {
           case PRV_U:
             cause = MISCREG_UCAUSE;
@@ -110,14 +131,55 @@ RiscvFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
             status.uie = 0;
             break;
           case PRV_S:
-            cause = MISCREG_SCAUSE;
-            epc = MISCREG_SEPC;
-            tvec = MISCREG_STVEC;
-            tval = MISCREG_STVAL;
-
-            status.spp = pp;
-            status.spie = status.sie;
-            status.sie = 0;
+              if (prvh == PRV_HS) {
+                  cause = MISCREG_SCAUSE;
+                  epc = MISCREG_SEPC;
+                  tvec = MISCREG_STVEC;
+                  //tval = MISCREG_STVAL;
+                  tval = MISCREG_VSTVAL;
+
+                  if (hstatus.vsxl == 1) {
+                      assert(0);
+
+                  } else {
+                      vsstatus.spp = pp;
+                      vsstatus.spie = vsstatus.sie;
+                      vsstatus.sie = 0;
+                  }
+
+                  tc->setMiscReg(MISCREG_VIRMODE, 1);
+                  if (isInterrupt())
+                      tc->setMiscReg(MISCREG_VSCAUSE, _code | (1L << 63));
+                  else
+                      tc->setMiscReg(MISCREG_VSCAUSE, _code);
+                  tc->setMiscReg(MISCREG_VSEPC, tc->pcState().instAddr());
+                  hs_mode_pc = true;
+              } else {
+                  cause = MISCREG_SCAUSE;
+                  epc = MISCREG_SEPC;
+                  tvec = MISCREG_STVEC;
+                  tval = MISCREG_STVAL;
+
+                  status.spp = pp;
+                  status.spie = status.sie;
+                  status.sie = 0;
+                  hstatus.gva =
+                      (!isInterrupt()) && (_code == INST_G_PAGE || _code == LOAD_G_PAGE || _code == STORE_G_PAGE ||
+                                           ((v) && ((0 <= _code && _code <= 7 && _code != 2) || _code == INST_PAGE ||
+                                                    _code == LOAD_PAGE || _code == STORE_PAGE)));
+                  hstatus.spv = v;
+                  if (v) {
+                      hstatus.spvp = pp;
+                  }
+                  if ((_code == INST_PAGE || _code == LOAD_PAGE || _code == STORE_PAGE ||
+                       _code == LOAD_ADDR_MISALIGNED || _code == STORE_ADDR_MISALIGNED || _code == INST_ACCESS ||
+                       _code == LOAD_ACCESS || _code == STORE_ACCESS) ||
+                      ((_code != INST_G_PAGE) && (_code != LOAD_G_PAGE) && (_code != STORE_G_PAGE))) {
+                      tc->setMiscReg(MISCREG_HTVAL, 0);
+                  }
+
+                  tc->setMiscReg(MISCREG_VIRMODE, 0);
+              }
             break;
           case PRV_M:
             cause = MISCREG_MCAUSE;
@@ -128,6 +190,12 @@ RiscvFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
             status.mpp = pp;
             status.mpie = status.mie;
             status.mie = 0;
+            status.gva =
+                (!isInterrupt()) && (_code == INST_G_PAGE || _code == LOAD_G_PAGE || _code == STORE_G_PAGE ||
+                                     ((v) && ((0 <= _code && _code <= 7 && _code != 2) || _code == INST_PAGE ||
+                                              _code == LOAD_PAGE || _code == STORE_PAGE)));
+            status.mpv = v;
+            tc->setMiscReg(MISCREG_VIRMODE, 0);
             break;
           default:
             panic("Unknown privilege mode %d.", prv);
@@ -140,14 +208,28 @@ RiscvFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
         if (isInterrupt()) {
            _cause |= (1L << 63);
         }
-        tc->setMiscReg(cause, _cause);
-        tc->setMiscReg(epc, tc->pcState().instAddr());
+
+        if (!hs_mode_pc) {
+            tc->setMiscReg(cause, _cause);
+            tc->setMiscReg(epc, tc->pcState().instAddr());
+        }
+
         if (_cause == INST_ILLEGAL)
             tc->setMiscReg(tval, 0);
         else
             tc->setMiscReg(tval, trap_value());
+        if (_code == INST_G_PAGE || _code == LOAD_G_PAGE || _code == STORE_G_PAGE) {
+            if (prv == PRV_S && (g_trap_value() != 0)) {
+                tc->setMiscReg(MISCREG_HTVAL, g_trap_value() >> 2);
+            } else if (g_trap_value() != 0) {
+                tc->setMiscReg(MISCREG_MTVAL2, g_trap_value() >> 2);
+            }
+        }
+
         tc->setMiscReg(MISCREG_PRV, prv);
         tc->setMiscReg(MISCREG_STATUS, status);
+        tc->setMiscReg(MISCREG_HSTATUS, hstatus);
+        tc->setMiscRegNoEffect(MISCREG_VSSTATUS, vsstatus);
         // Temporarily mask NMI while we're in NMI handler. Otherweise, the
         // checkNonMaskableInterrupt will always return true and we'll be
         // stucked in an infinite loop.
@@ -156,8 +238,16 @@ RiscvFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
         }
 
         // Set PC to fault handler address
-        Addr addr = mbits(tc->readMiscReg(tvec), 63, 2);
-        if (isInterrupt() && bits(tc->readMiscReg(tvec), 1, 0) == 1)
+        Addr addr = 0;
+        auto addr_tvec = tc->readMiscReg(tvec);
+        if (!hs_mode_pc) {
+            addr = mbits(tc->readMiscReg(tvec), 63, 2);
+        } else {
+            addr = mbits(tc->readMiscReg(MISCREG_VSTVEC), 63, 2);
+            addr_tvec = tc->readMiscReg(MISCREG_VSTVEC);
+        }
+
+        if (isInterrupt() && bits(addr_tvec, 1, 0) == 1)
             addr += 4 * _code;
         pc_state.set(addr);
         tc->pcState(pc_state);
@@ -225,5 +315,11 @@ SyscallFault::invokeSE(ThreadContext *tc, const StaticInstPtr &inst)
     tc->getSystemPtr()->workload->syscall(tc);
 }
 
+void
+HVFault::invokeSE(ThreadContext *tc, const StaticInstPtr &inst)
+{
+    panic("HVFault at pc %s", tc->pcState());
+}
+
 } // namespace RiscvISA
 } // namespace gem5

src/arch/riscv/faults.hh

@@ -78,11 +78,17 @@ enum ExceptionCode : uint64_t
     AMO_ACCESS = 7,
     ECALL_USER = 8,
     ECALL_SUPER = 9,
+    ECALL_VS = 10,  // ecall from vs-mode h-extention
     ECALL_MACHINE = 11,
     INST_PAGE = 12,
     LOAD_PAGE = 13,
     STORE_PAGE = 15,
     AMO_PAGE = 15,
+    INST_G_PAGE = 20,
+    LOAD_G_PAGE = 21,
+    VIRTUAL_INST = 22,
+    STORE_G_PAGE = 23,
+    AMO_G_PAGE = 23,
 
     INT_SOFTWARE_USER = 0,
     INT_SOFTWARE_SUPER = 1,
@@ -120,8 +126,9 @@ class RiscvFault : public FaultBase
     {
         return _fault_type == FaultType::NON_MASKABLE_INTERRUPT;
     }
-    ExceptionCode exception() const { return _code; }
+    uint64_t exception() const override{ return _code; }
     virtual RegVal trap_value() const { return 0; }
+    virtual RegVal g_trap_value() const { return 0; }
 
     virtual void invokeSE(ThreadContext *tc, const StaticInstPtr &inst);
     void invoke(ThreadContext *tc, const StaticInstPtr &inst) override;
@@ -228,13 +235,15 @@ class AddressFault : public RiscvFault
 {
   private:
     const Addr _addr;
+    const Addr _gPaddr;
 
   public:
-    AddressFault(const Addr addr, ExceptionCode code)
-        : RiscvFault("Address", FaultType::OTHERS, code), _addr(addr)
+    AddressFault(const Addr addr,const Addr gPaddr, ExceptionCode code)
+        : RiscvFault("Address", FaultType::OTHERS, code), _addr(addr),_gPaddr(gPaddr)
     {}
 
     RegVal trap_value() const override { return _addr; }
+    RegVal g_trap_value() const override { return _gPaddr; }
 };
 
 class BreakpointFault : public RiscvFault
@@ -277,6 +286,12 @@ class SyscallFault : public RiscvFault
     void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override;
 };
 
+class HVFault : public RiscvFault
+{
+  public:
+    HVFault() : RiscvFault("System call", FaultType::OTHERS, VIRTUAL_INST) {}
+    void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override;
+};
 } // namespace RiscvISA
 } // namespace gem5
 

src/arch/riscv/insts/standard.hh

@@ -129,8 +129,9 @@ class CSROp : public RiscvStaticInst
             auto mask_it = CSRMasks.find(csr);
             if (mask_it == CSRMasks.end())
                 maskVal = mask(64);
-            else
+            else {
                 maskVal = mask_it->second;
+            }
         }
 
         if (csr == CSR_SATP) {