arch-riscv: Fix zero reg RegClass

OpenXiangShan · Jun 18, 2024 · d97fe95 · d97fe95
1 parent 89e3f2b
commit d97fe95
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/src/arch/riscv/regs/int.hh b/src/arch/riscv/regs/int.hh
@@ -80,7 +80,7 @@ enum : RegIndex
 };
 
 inline constexpr RegId
-    Zero(IntRegClass, _ZeroIdx),
+    Zero(InvalidRegClass, _ZeroIdx),
     Ra(IntRegClass, _RaIdx),
     Sp(IntRegClass, _SpIdx),
     Gp(IntRegClass, _GpIdx),