Merge pull request #149 from OpenXiangShan/prepare-rtl-tile-cosim

Prepare rtl tile cosim

build_tools/cxx_config_cc.py

@@ -287,6 +287,8 @@ def cxx_bool(b):
 code.indent()
 if hasattr(sim_object, 'abstract') and sim_object.abstract:
     code('return nullptr;')
+elif issubclass(sim_object, m5.objects.SystemC.SystemC_ScModule):
+    code('return nullptr;')
 else:
     code('return this->create();')
 code.dedent()

configs/topologies/CustomMesh.py

@@ -1,4 +1,4 @@
-# Copyright (c) 2021 ARM Limited
+# Copyright (c) 2021,2022 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -304,7 +304,7 @@ def check_same(val, curr):
         self.distributeNodes(hnf_params, hnf_nodes)
 
         # Place CHI_MN on the mesh
-        self.distributeNodes(options, mn_params, mn_nodes)
+        self.distributeNodes(mn_params, mn_nodes)
 
         # Place CHI_SNF_MainMem on the mesh
         self.distributeNodes(mem_params, mem_nodes)
@@ -319,6 +319,10 @@ def check_same(val, curr):
         # Set up
         network.int_links = self._int_links
         network.ext_links = self._ext_links
+        # fix Routers being set as link child
+        for r in self._routers:
+            if r.has_parent():
+                r.get_parent().clear_child(r.get_name())
         network.routers = self._routers
 
         pairing = getattr(options, 'pairing', None)

src/mem/ruby/common/HasDownStream.hh

@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2024 Beijing Institute of Open Source Chip
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Author: Yaoyang Zhou
+ *
+ */
+#ifndef __MEM_RUBY_COMMON_HASDOWNSTREAM_HH__
+#define __MEM_RUBY_COMMON_HASDOWNSTREAM_HH__
+
+#include "base/addr_range.hh"
+#include "base/addr_range_map.hh"
+#include "mem/ruby/common/MachineID.hh"
+#include "mem/ruby/common/NetDest.hh"
+
+namespace gem5
+{
+
+namespace ruby
+{
+
+class HasDownStream
+{
+  protected:
+    std::unordered_map<MachineType, AddrRangeMap<MachineID, 3>>
+      downstreamAddrMap;
+
+    NetDest downstreamDestinations;
+  public:
+    /**
+     * Maps an address to the correct dowstream MachineID (i.e. the component
+     * in the next level of the cache hierarchy towards memory)
+     *
+     * This function uses the local list of possible destinations instead of
+     * querying the network.
+     *
+     * @param the destination address
+     * @param the type of the destination (optional)
+     * @return the MachineID of the destination
+     */
+    MachineID mapAddressToDownstreamMachine(Addr addr,
+                                    MachineType mtype = MachineType_NUM) const
+    {
+        if (mtype == MachineType_NUM) {
+            // map to the first match
+            for (const auto &i : downstreamAddrMap) {
+                const auto mapping = i.second.contains(addr);
+                if (mapping != i.second.end())
+                    return mapping->second;
+            }
+        } else {
+            const auto i = downstreamAddrMap.find(mtype);
+            if (i != downstreamAddrMap.end()) {
+                const auto mapping = i->second.contains(addr);
+                if (mapping != i->second.end())
+                    return mapping->second;
+            }
+        }
+        fatal("Couldn't find mapping for address %x mtype=%s\n", addr, mtype);
+    }
+
+    /** List of downstream destinations (towards memory) */
+    const NetDest& allDownstreamDest() const { return downstreamDestinations; }
+};
+}
+}
+
+#endif // __MEM_RUBY_COMMON_HASDOWNSTREAM_HH__

src/mem/ruby/slicc_interface/AbstractController.cc

@@ -423,31 +423,6 @@ AbstractController::mapAddressToMachine(Addr addr, MachineType mtype) const
     return mach;
 }
 
-MachineID
-AbstractController::mapAddressToDownstreamMachine(Addr addr, MachineType mtype)
-const
-{
-    if (mtype == MachineType_NUM) {
-        // map to the first match
-        for (const auto &i : downstreamAddrMap) {
-            const auto mapping = i.second.contains(addr);
-            if (mapping != i.second.end())
-                return mapping->second;
-        }
-    }
-    else {
-        const auto i = downstreamAddrMap.find(mtype);
-        if (i != downstreamAddrMap.end()) {
-            const auto mapping = i->second.contains(addr);
-            if (mapping != i->second.end())
-                return mapping->second;
-        }
-    }
-    fatal("%s: couldn't find mapping for address %x mtype=%s\n",
-        name(), addr, mtype);
-}
-
-
 void
 AbstractController::memRespQueueDequeued() {
     if (m_mem_ctrl_waiting_retry && !mRetryRespEvent.scheduled()) {

src/mem/ruby/slicc_interface/AbstractController.hh

@@ -54,6 +54,7 @@
 #include "mem/ruby/common/Address.hh"
 #include "mem/ruby/common/Consumer.hh"
 #include "mem/ruby/common/DataBlock.hh"
+#include "mem/ruby/common/HasDownStream.hh"
 #include "mem/ruby/common/Histogram.hh"
 #include "mem/ruby/common/MachineID.hh"
 #include "mem/ruby/network/MessageBuffer.hh"
@@ -80,7 +81,7 @@ class RejectException: public std::exception
     { return "Port rejected message based on type"; }
 };
 
-class AbstractController : public ClockedObject, public Consumer
+class AbstractController : public ClockedObject, public Consumer, public HasDownStream
 {
   public:
     PARAMS(RubyController);
@@ -209,23 +210,6 @@ class AbstractController : public ClockedObject, public Consumer
      */
     MachineID mapAddressToMachine(Addr addr, MachineType mtype) const;
 
-    /**
-     * Maps an address to the correct dowstream MachineID (i.e. the component
-     * in the next level of the cache hierarchy towards memory)
-     *
-     * This function uses the local list of possible destinations instead of
-     * querying the network.
-     *
-     * @param the destination address
-     * @param the type of the destination (optional)
-     * @return the MachineID of the destination
-     */
-    MachineID mapAddressToDownstreamMachine(Addr addr,
-                                    MachineType mtype = MachineType_NUM) const;
-
-    /** List of downstream destinations (towards memory) */
-    const NetDest& allDownstreamDest() const { return downstreamDestinations; }
-
     /** List of upstream destinations (towards the CPU) */
     const NetDest& allUpstreamDest() const { return upstreamDestinations; }
 
@@ -456,10 +440,6 @@ class AbstractController : public ClockedObject, public Consumer
     /** The address range to which the controller responds on the CPU side. */
     const AddrRangeList addrRanges;
 
-    std::unordered_map<MachineType, AddrRangeMap<MachineID, 3>>
-      downstreamAddrMap;
-
-    NetDest downstreamDestinations;
     NetDest upstreamDestinations;
 
     void sendRetryRespToMem();

util/cxx_config/Makefile

@@ -33,7 +33,7 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-ARCH = ARM
+ARCH ?= ARM
 VARIANT = opt
 
 CXXFLAGS = -I../../build/$(ARCH) -L../../build/$(ARCH) -DTRACING_ON=1