[RISC-V] Allow enabling CFG_TEE_CORE_DEBUG #7028
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lyctw
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etienne-lms
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core/arch/riscv/mm/core_mmu_arch.c
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| @@ -466,6 +466,7 @@ bool arch_va2pa_helper(void *va, paddr_t *pa) | |||
| int level = 0; | |||
| unsigned int idx = 0; | |||
| struct mmu_partition *prtn = core_mmu_get_prtn(); | |||
| vaddr_t offset_mask = 0; /* page offset mask */ | |||
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nitpicking: I don't think the inline comment is really useful.
core/mm/core_mmu.c
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| * Moreover, if arch_va2pa_helper() returns true, it implies | ||
| * the va2pa mapping is matched, no need to check again. | ||
| */ | ||
| #if defined(CFG_TEE_CORE_DEBUG) && !defined(RV64) |
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Only for RV64, not for RV32? it seems the implementation of the same for these 2 configurations.
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yes, fixed it by using gcc pre-defined macro !defined(__riscv)
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Acked-by: Etienne Carriere <[email protected]> for the series.
|
CI Code style error report seems due to a false positive. |
Any level of PTE may be a leaf PTE in RISC-V page table, if the
page is not 4KiB, the page offset should be extended to VPN fields
of virtual address.
e.g. on Sv39, if there is a leaf PTE on level-1 (2MiB megapage),
it maps to physical page with (va[20:12] | va[11:0]) as the page
offset.
Sv39 Virtual address:
|<--- superpage offset --->|
38_______30_29______21|20______12_11____________0|
| VPN[2] | VPN[1] | VPN[0] | page offset |
‾‾‾‾9‾‾‾‾‾‾‾‾‾‾9‾‾‾‾‾|‾‾‾‾9‾‾‾‾‾‾‾‾‾‾‾‾12‾‾‾‾‾‾‾|
| |
Physical address: | |
| |
55___________30_29______21|20______12_11____________0|
| PPN[2] | PPN[1] | PPN[0] | page offset |
‾‾‾‾‾‾26‾‾‾‾‾‾‾‾‾‾‾9‾‾‾‾‾'‾‾‾‾9‾‾‾‾‾‾‾‾‾‾‾‾12‾‾‾‾‾‾‾'
Signed-off-by: Yu Chien Peter Lin <[email protected]>
Reviewed-by: Alvin Chang <[email protected]>
Tested-by: Alvin Chang <[email protected]>
Acked-by: Etienne Carriere <[email protected]>
Fix the compile error in the bit_test() macro, which mistakenly uses the address of g_asid as the parameter. Signed-off-by: Yu Chien Peter Lin <[email protected]> Reviewed-by: Alvin Chang <[email protected]> Tested-by: Alvin Chang <[email protected]> Acked-by: Etienne Carriere <[email protected]>
The function hasn't been implemented for RISC-V, so move the core_mmu_user_va_range_is_defined() definition to generic core_mmu.h and function implementations to arch-specific files. Also, update the assertions where checks if user va range is defined. Signed-off-by: Yu Chien Peter Lin <[email protected]> Reviewed-by: Alvin Chang <[email protected]> Tested-by: Alvin Chang <[email protected]> Acked-by: Etienne Carriere <[email protected]>
The arch_va2pa_helper() in the RISC-V implements a software page table
walker. It requires phys_to_virt() to convert the physical page on the
PTE to the virtual address of the next level page table. The process
can lead to a stack overflow caused by indirect recursion as below:
phys_to_virt() <--------------------------------.
-> check_va_matches_pa() |
-> virt_to_phys() |
-> arch_va2pa_helper() |
-> core_mmu_xlat_table_entry_pa2va()-'
As arch_va2pa_helper() can return true if va matches pa, we
don't use and check_va_matches_pa() when CFG_TEE_CORE_DEBUG
is enabled.
Signed-off-by: Yu Chien Peter Lin <[email protected]>
Reviewed-by: Alvin Chang <[email protected]>
Tested-by: Alvin Chang <[email protected]>
Acked-by: Etienne Carriere <[email protected]>
Allow enabling CFG_TEE_CORE_DEBUG to make assertions useful. Signed-off-by: Yu Chien Peter Lin <[email protected]> Reviewed-by: Alvin Chang <[email protected]> Tested-by: Alvin Chang <[email protected]> Acked-by: Etienne Carriere <[email protected]>
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This series enables CFG_TEE_CORE_DEBUG, a crucial feature for early error detection on RISC-V platforms, such as assertions.