GitHub - Grvzard/MIPS-cpu: a 5-stage pipeline cpu supports a subset of MIPS32, implemented in logisim and chisel respectively

Grvzard / MIPS-cpu Public

a 5-stage pipeline cpu supports a subset of MIPS32, implemented in logisim and chisel respectively

Notifications

Name		Name	Last commit message	Last commit date
Latest commit History 80 Commits
.vscode		.vscode
project		project
reference		reference
src		src
testbench		testbench
tests		tests
verilog-old		verilog-old
.gitignore		.gitignore
.mill-version		.mill-version
.scalafmt.conf		.scalafmt.conf
ALUctr-hdl.txt		ALUctr-hdl.txt
ALUctr.txt		ALUctr.txt
MIPS-logisim.circ		MIPS-logisim.circ
Makefile		Makefile
build.sbt		build.sbt
build.sc		build.sc
design.txt		design.txt
instructions.pdf		instructions.pdf
multipliers.circ		multipliers.circ
snapshot.png		snapshot.png