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design.txt
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design.txt
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- adder32 overflow flag
truth table of (A[31], B[31], 31st Ci, 31st Co, F[31])
A B Ci F Co
0 0 0 0 0
0 0 1 1 0 (overflow)
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1 (overflow)
1 1 1 1 1
tuple (A, B, F) identifiable
overflow <==> Ci ^ Co <==> (~A & ~B & F) | (A & B & ~F)
- flush a stage's result
(to prevent reg-files from being modified by this result)
(pc, 32gpr)
IF: instr <- 0
ID: RegWr <- 0, MemWr <- 0, Mem2Reg <- 0, MDUop <- 0000, ALUop <- (not 00001 or 10001)
EX: RegWr <- 0, MemWr <- 0, Mem2Reg <- 0, Overflow <- 0
- slt/sltu, the implementation of less-then comparator
slt: A < B <==> A - B < 0 <==> Sign & ~Overflow | Overflow & ~Sign <==> Sign ^ Overflow
sltu: A < B -> B + (-B) = (F:0, Cout:1) -> A + (-B) < (F:0, Cout:1) <==> ~Cout
- jumps and branches (one delay slot)
OP CODE
beq 000
bgez 001
bgezal 010
bgtz 011
blez 100
bltz 101
bltzal 110
bne 111
beq/bne: ~^BranchOp
bgezal/bltzal: Branch & RegWr
jr/jalr: Jump & Rtype
j: Jump & ~Rtype & ~RegWr
jal: Jump & ~Rtype & RegWr
in stages other than ID, Branch means Branch or Jump
_al(branch/jump and link) instructions produce RegWr and generate ALUop "addu"
we generalize it to all branchs generate "addu"
- MDU (pseudo Multiply/Divide Unit)
OP CODE FUNC
multu 1000 011001 sp
mult 1001 011000 sp
msubu 1010 000101 sp2
msub 1011 000100 sp2
maddu 1100 000001 sp2
madd 1101 000000 sp2
divu 1110 011011 sp
div 1111 011010 sp
mtlo 0001 010011 sp
mthi 0010 010001 sp
mul generates the same opcode as mult, but with RegWr and MovAcc
act as a 3-cycle Multiplier
- SPECIAL2 commands
OP FUNC
clz 100000
clo 100001
msubu 000101
msub 000100
maddu 000001
madd 000000
mul 000010
- COP0 commands
mtc0 mfc0
- a general-purpose signal Sel by instruction-decoder
movn/movz: in ID, 1 for not-zero
mfhi/mflo: in EX, 1 for hi
signed/unsigned load: in Mem, 1 for sign-extend
- Address Alignment control signal (AAop)
OP CODE WEMASK
00 b 0001
01 w 1111
10 uw 1111
11 h 0011
-- multiplier
(y[2i+1], y[2i], t[i]) action t[i+1]
0 0 0 +0 0
0 0 1 +x 0
0 1 0 +x 0
0 1 1 +2x 0
1 0 0 +2x 0
1 0 1 -x 1
1 1 0 -x 1
1 1 1 +0 1
(y[31], y[30], t[16]) action(Signed)
0 0 0 0
0 0 1 +x
0 1 0 +x
0 1 1 +2x
1 0 0 +2x-4x
1 0 1 -x
1 1 0 -x
1 1 1 +0