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InstCountCI: Update
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Signed-off-by: Alyssa Rosenzweig <[email protected]>
alyssarosenzweig committed Mar 29, 2024
1 parent c9f972a commit 0daed2d
Showing 2 changed files with 108 additions and 132 deletions.
88 changes: 38 additions & 50 deletions unittests/InstructionCountCI/FlagM/PrimaryGroup.json
Original file line number Diff line number Diff line change
@@ -1297,13 +1297,12 @@
]
},
"shl al, 1": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 7,
"Comment": "GROUP2 0xd0 /4",
"ExpectedArm64ASM": [
"uxtb w20, w4",
"lsl w21, w20, #1",
"bfxil x4, x21, #0, #8",
"uxtb w26, w21",
"lsl w26, w20, #1",
"bfxil x4, x26, #0, #8",
"cmn wzr, w26, lsl #24",
"rmif x20, #6, #nzCv",
"eor w20, w26, w20",
@@ -1475,13 +1474,12 @@
]
},
"shl ax, 1": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 7,
"Comment": "GROUP2 0xd1 /4",
"ExpectedArm64ASM": [
"uxth w20, w4",
"lsl w21, w20, #1",
"bfxil x4, x21, #0, #16",
"uxth w26, w21",
"lsl w26, w20, #1",
"bfxil x4, x26, #0, #16",
"cmn wzr, w26, lsl #16",
"rmif x20, #14, #nzCv",
"eor w20, w26, w20",
@@ -1585,21 +1583,20 @@
]
},
"rol al, cl": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 12,
"Comment": "GROUP2 0xd2 /0",
"ExpectedArm64ASM": [
"uxtb w20, w4",
"uxtb w21, w5",
"and w21, w21, #0x1f",
"bfi w20, w20, #8, #8",
"bfi w20, w20, #16, #16",
"mov w22, #0x20",
"sub w22, w22, w21",
"neg w22, w21",
"ror w20, w20, w22",
"bfxil x4, x20, #0, #8",
"cbz x21, #+0x10",
"rmif x20, #63, #nzCv",
"eor w20, w20, w20, lsr #7",
"rmif x4, #63, #nzCv",
"eor w20, w4, w4, lsr #7",
"rmif x20, #0, #nzcV"
]
},
@@ -1615,8 +1612,8 @@
"ror w20, w20, w21",
"bfxil x4, x20, #0, #8",
"cbz x21, #+0x10",
"rmif x20, #6, #nzCv",
"eor w20, w20, w20, lsr #1",
"rmif x4, #6, #nzCv",
"eor w20, w4, w4, lsr #1",
"rmif x20, #6, #nzcV"
]
},
@@ -1678,14 +1675,13 @@
]
},
"shl al, cl": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 13,
"Comment": "GROUP2 0xd2 /4",
"ExpectedArm64ASM": [
"uxtb w20, w4",
"uxtb w21, w5",
"lsl w22, w20, w21",
"bfxil x4, x22, #0, #8",
"uxtb w22, w22",
"cbz x21, #+0x24",
"cmn wzr, w22, lsl #24",
"mov w23, #0x8",
@@ -1733,52 +1729,47 @@
]
},
"rol ax, cl": {
"ExpectedInstructionCount": 12,
"ExpectedInstructionCount": 11,
"Comment": "GROUP2 0xd3 /0",
"ExpectedArm64ASM": [
"uxth w20, w4",
"uxth w21, w5",
"and w21, w21, #0x1f",
"bfi w20, w20, #16, #16",
"mov w22, #0x20",
"sub w22, w22, w21",
"neg w22, w21",
"ror w20, w20, w22",
"bfxil x4, x20, #0, #16",
"cbz x21, #+0x10",
"rmif x20, #63, #nzCv",
"eor w20, w20, w20, lsr #15",
"rmif x4, #63, #nzCv",
"eor w20, w4, w4, lsr #15",
"rmif x20, #0, #nzcV"
]
},
"rol eax, cl": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 9,
"Comment": "GROUP2 0xd3 /0",
"ExpectedArm64ASM": [
"mov w20, w4",
"mov w21, w5",
"and w21, w21, #0x1f",
"mov w22, #0x20",
"sub w22, w22, w21",
"ror w20, w20, w22",
"mov x4, x20",
"neg w22, w21",
"ror w4, w20, w22",
"cbz x21, #+0x10",
"rmif x20, #63, #nzCv",
"eor w20, w20, w20, lsr #31",
"rmif x4, #63, #nzCv",
"eor w20, w4, w4, lsr #31",
"rmif x20, #0, #nzcV"
]
},
"rol rax, cl": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 7,
"Comment": "GROUP2 0xd3 /0",
"ExpectedArm64ASM": [
"and x20, x5, #0x3f",
"mov w21, #0x40",
"sub x21, x21, x20",
"ror x21, x4, x21",
"mov x4, x21",
"neg x21, x20",
"ror x4, x4, x21",
"cbz x20, #+0x10",
"rmif x21, #63, #nzCv",
"eor x20, x21, x21, lsr #63",
"rmif x4, #63, #nzCv",
"eor x20, x4, x4, lsr #63",
"rmif x20, #0, #nzcV"
]
},
@@ -1793,36 +1784,34 @@
"ror w20, w20, w21",
"bfxil x4, x20, #0, #16",
"cbz x21, #+0x10",
"rmif x20, #14, #nzCv",
"eor w20, w20, w20, lsr #1",
"rmif x4, #14, #nzCv",
"eor w20, w4, w4, lsr #1",
"rmif x20, #14, #nzcV"
]
},
"ror eax, cl": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 8,
"Comment": "GROUP2 0xd3 /1",
"ExpectedArm64ASM": [
"mov w20, w4",
"mov w21, w5",
"and w21, w21, #0x1f",
"ror w20, w20, w21",
"mov x4, x20",
"ror w4, w20, w21",
"cbz x21, #+0x10",
"rmif x20, #30, #nzCv",
"eor w20, w20, w20, lsr #1",
"rmif x4, #30, #nzCv",
"eor w20, w4, w4, lsr #1",
"rmif x20, #30, #nzcV"
]
},
"ror rax, cl": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 6,
"Comment": "GROUP2 0xd3 /1",
"ExpectedArm64ASM": [
"and x20, x5, #0x3f",
"ror x21, x4, x20",
"mov x4, x21",
"ror x4, x4, x20",
"cbz x20, #+0x10",
"rmif x21, #62, #nzCv",
"eor x20, x21, x21, lsr #1",
"rmif x4, #62, #nzCv",
"eor x20, x4, x4, lsr #1",
"rmif x20, #62, #nzcV"
]
},
@@ -1963,14 +1952,13 @@
]
},
"shl ax, cl": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 13,
"Comment": "GROUP2 0xd3 /4",
"ExpectedArm64ASM": [
"uxth w20, w4",
"uxth w21, w5",
"lsl w22, w20, w21",
"bfxil x4, x22, #0, #16",
"uxth w22, w22",
"cbz x21, #+0x24",
"cmn wzr, w22, lsl #16",
"mov w23, #0x10",
152 changes: 70 additions & 82 deletions unittests/InstructionCountCI/PrimaryGroup.json
Original file line number Diff line number Diff line change
@@ -1494,13 +1494,12 @@
]
},
"shl al, 1": {
"ExpectedInstructionCount": 12,
"ExpectedInstructionCount": 11,
"Comment": "GROUP2 0xd0 /4",
"ExpectedArm64ASM": [
"uxtb w20, w4",
"lsl w21, w20, #1",
"bfxil x4, x21, #0, #8",
"uxtb w26, w21",
"lsl w26, w20, #1",
"bfxil x4, x26, #0, #8",
"cmn wzr, w26, lsl #24",
"mrs x21, nzcv",
"ubfx x22, x20, #7, #1",
@@ -1761,13 +1760,12 @@
]
},
"shl ax, 1": {
"ExpectedInstructionCount": 12,
"ExpectedInstructionCount": 11,
"Comment": "GROUP2 0xd1 /4",
"ExpectedArm64ASM": [
"uxth w20, w4",
"lsl w21, w20, #1",
"bfxil x4, x21, #0, #16",
"uxth w26, w21",
"lsl w26, w20, #1",
"bfxil x4, x26, #0, #16",
"cmn wzr, w26, lsl #16",
"mrs x21, nzcv",
"ubfx x22, x20, #15, #1",
@@ -1904,26 +1902,25 @@
]
},
"rol al, cl": {
"ExpectedInstructionCount": 18,
"ExpectedInstructionCount": 17,
"Comment": "GROUP2 0xd2 /0",
"ExpectedArm64ASM": [
"uxtb w20, w4",
"uxtb w21, w5",
"and w21, w21, #0x1f",
"bfi w20, w20, #8, #8",
"bfi w20, w20, #16, #16",
"mov w22, #0x20",
"sub w22, w22, w21",
"neg w22, w21",
"ror w20, w20, w22",
"bfxil x4, x20, #0, #8",
"cbz x21, #+0x24",
"mrs x21, nzcv",
"and w21, w21, #0xc0000000",
"ubfx x22, x20, #0, #1",
"orr w21, w21, w22, lsl #29",
"eor w20, w20, w20, lsr #7",
"ubfx x20, x20, #0, #1",
"orr w20, w21, w20, lsl #28",
"mrs x20, nzcv",
"and w20, w20, #0xc0000000",
"ubfx x21, x4, #0, #1",
"orr w20, w20, w21, lsl #29",
"eor w21, w4, w4, lsr #7",
"ubfx x21, x21, #0, #1",
"orr w20, w20, w21, lsl #28",
"msr nzcv, x20"
]
},
@@ -1939,13 +1936,13 @@
"ror w20, w20, w21",
"bfxil x4, x20, #0, #8",
"cbz x21, #+0x24",
"mrs x21, nzcv",
"and w21, w21, #0xc0000000",
"ubfx x22, x20, #7, #1",
"orr w21, w21, w22, lsl #29",
"eor w20, w20, w20, lsr #1",
"ubfx x20, x20, #6, #1",
"orr w20, w21, w20, lsl #28",
"mrs x20, nzcv",
"and w20, w20, #0xc0000000",
"ubfx x21, x4, #7, #1",
"orr w20, w20, w21, lsl #29",
"eor w21, w4, w4, lsr #1",
"ubfx x21, x21, #6, #1",
"orr w20, w20, w21, lsl #28",
"msr nzcv, x20"
]
},
@@ -2021,14 +2018,13 @@
]
},
"shl al, cl": {
"ExpectedInstructionCount": 18,
"ExpectedInstructionCount": 17,
"Comment": "GROUP2 0xd2 /4",
"ExpectedArm64ASM": [
"uxtb w20, w4",
"uxtb w21, w5",
"lsl w22, w20, w21",
"bfxil x4, x22, #0, #8",
"uxtb w22, w22",
"cbz x21, #+0x34",
"cmn wzr, w22, lsl #24",
"mrs x23, nzcv",
@@ -2087,65 +2083,60 @@
]
},
"rol ax, cl": {
"ExpectedInstructionCount": 17,
"ExpectedInstructionCount": 16,
"Comment": "GROUP2 0xd3 /0",
"ExpectedArm64ASM": [
"uxth w20, w4",
"uxth w21, w5",
"and w21, w21, #0x1f",
"bfi w20, w20, #16, #16",
"mov w22, #0x20",
"sub w22, w22, w21",
"neg w22, w21",
"ror w20, w20, w22",
"bfxil x4, x20, #0, #16",
"cbz x21, #+0x24",
"mrs x21, nzcv",
"and w21, w21, #0xc0000000",
"ubfx x22, x20, #0, #1",
"orr w21, w21, w22, lsl #29",
"eor w20, w20, w20, lsr #15",
"ubfx x20, x20, #0, #1",
"orr w20, w21, w20, lsl #28",
"mrs x20, nzcv",
"and w20, w20, #0xc0000000",
"ubfx x21, x4, #0, #1",
"orr w20, w20, w21, lsl #29",
"eor w21, w4, w4, lsr #15",
"ubfx x21, x21, #0, #1",
"orr w20, w20, w21, lsl #28",
"msr nzcv, x20"
]
},
"rol eax, cl": {
"ExpectedInstructionCount": 16,
"ExpectedInstructionCount": 14,
"Comment": "GROUP2 0xd3 /0",
"ExpectedArm64ASM": [
"mov w20, w4",
"mov w21, w5",
"and w21, w21, #0x1f",
"mov w22, #0x20",
"sub w22, w22, w21",
"ror w20, w20, w22",
"mov x4, x20",
"neg w22, w21",
"ror w4, w20, w22",
"cbz x21, #+0x24",
"mrs x21, nzcv",
"and w21, w21, #0xc0000000",
"ubfx x22, x20, #0, #1",
"orr w21, w21, w22, lsl #29",
"eor w20, w20, w20, lsr #31",
"ubfx x20, x20, #0, #1",
"orr w20, w21, w20, lsl #28",
"mrs x20, nzcv",
"and w20, w20, #0xc0000000",
"ubfx x21, x4, #0, #1",
"orr w20, w20, w21, lsl #29",
"eor w21, w4, w4, lsr #31",
"ubfx x21, x21, #0, #1",
"orr w20, w20, w21, lsl #28",
"msr nzcv, x20"
]
},
"rol rax, cl": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 12,
"Comment": "GROUP2 0xd3 /0",
"ExpectedArm64ASM": [
"and x20, x5, #0x3f",
"mov w21, #0x40",
"sub x21, x21, x20",
"ror x21, x4, x21",
"mov x4, x21",
"neg x21, x20",
"ror x4, x4, x21",
"cbz x20, #+0x24",
"mrs x20, nzcv",
"and w20, w20, #0xc0000000",
"ubfx x22, x21, #0, #1",
"orr w20, w20, w22, lsl #29",
"eor x21, x21, x21, lsr #63",
"ubfx x21, x4, #0, #1",
"orr w20, w20, w21, lsl #29",
"eor x21, x4, x4, lsr #63",
"ubfx x21, x21, #0, #1",
"orr w20, w20, w21, lsl #28",
"msr nzcv, x20"
@@ -2162,49 +2153,47 @@
"ror w20, w20, w21",
"bfxil x4, x20, #0, #16",
"cbz x21, #+0x24",
"mrs x21, nzcv",
"and w21, w21, #0xc0000000",
"ubfx x22, x20, #15, #1",
"orr w21, w21, w22, lsl #29",
"eor w20, w20, w20, lsr #1",
"ubfx x20, x20, #14, #1",
"orr w20, w21, w20, lsl #28",
"mrs x20, nzcv",
"and w20, w20, #0xc0000000",
"ubfx x21, x4, #15, #1",
"orr w20, w20, w21, lsl #29",
"eor w21, w4, w4, lsr #1",
"ubfx x21, x21, #14, #1",
"orr w20, w20, w21, lsl #28",
"msr nzcv, x20"
]
},
"ror eax, cl": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 13,
"Comment": "GROUP2 0xd3 /1",
"ExpectedArm64ASM": [
"mov w20, w4",
"mov w21, w5",
"and w21, w21, #0x1f",
"ror w20, w20, w21",
"mov x4, x20",
"ror w4, w20, w21",
"cbz x21, #+0x24",
"mrs x21, nzcv",
"and w21, w21, #0xc0000000",
"ubfx x22, x20, #31, #1",
"orr w21, w21, w22, lsl #29",
"eor w20, w20, w20, lsr #1",
"ubfx x20, x20, #30, #1",
"orr w20, w21, w20, lsl #28",
"mrs x20, nzcv",
"and w20, w20, #0xc0000000",
"ubfx x21, x4, #31, #1",
"orr w20, w20, w21, lsl #29",
"eor w21, w4, w4, lsr #1",
"ubfx x21, x21, #30, #1",
"orr w20, w20, w21, lsl #28",
"msr nzcv, x20"
]
},
"ror rax, cl": {
"ExpectedInstructionCount": 12,
"ExpectedInstructionCount": 11,
"Comment": "GROUP2 0xd3 /1",
"ExpectedArm64ASM": [
"and x20, x5, #0x3f",
"ror x21, x4, x20",
"mov x4, x21",
"ror x4, x4, x20",
"cbz x20, #+0x24",
"mrs x20, nzcv",
"and w20, w20, #0xc0000000",
"lsr x22, x21, #63",
"orr w20, w20, w22, lsl #29",
"eor x21, x21, x21, lsr #1",
"lsr x21, x4, #63",
"orr w20, w20, w21, lsl #29",
"eor x21, x4, x4, lsr #1",
"ubfx x21, x21, #62, #1",
"orr w20, w20, w21, lsl #28",
"msr nzcv, x20"
@@ -2389,14 +2378,13 @@
]
},
"shl ax, cl": {
"ExpectedInstructionCount": 18,
"ExpectedInstructionCount": 17,
"Comment": "GROUP2 0xd3 /4",
"ExpectedArm64ASM": [
"uxth w20, w4",
"uxth w21, w5",
"lsl w22, w20, w21",
"bfxil x4, x22, #0, #16",
"uxth w22, w22",
"cbz x21, #+0x34",
"cmn wzr, w22, lsl #16",
"mrs x23, nzcv",

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