Mtl-h update FSP 4122_21 #566
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Change-Id: I5fde994b9dc05469b08c6a14ecd6b971a25e365f Signed-off-by: Michał Kopeć <[email protected]>
Change-Id: I0626867dc882e77b1b5018b0851ca9a2c9e57ff0 Signed-off-by: Michał Kopeć <[email protected]>
Change-Id: I161febbca12cd116a27167138a6ab523a644763c Signed-off-by: Michał Kopeć <[email protected]>
Change-Id: I500f4b502e1ac58e437e53bd0e4cb934c7bb3bbc Signed-off-by: Michał Kopeć <[email protected]>
Change-Id: Ib7c537a1e94fdeaabc65fcabeee17fff8a0e753a Signed-off-by: Michał Kopeć <[email protected]>
Needed for Windows not to BSOD due to malformed ACPI tables. Change-Id: Id8a8acea43d0d4615fb26ed66fddda2e74ca0f28 Signed-off-by: Michał Kopeć <[email protected]>
… option Change-Id: I91d2133bf6a9f2f9ca355f1af2c0d454795d6ef8 Signed-off-by: Michał Kopeć <[email protected]>
Change-Id: I082a4459afd80c328c9233b37ddd6f3a2c5bc528 Signed-off-by: Michał Kopeć <[email protected]>
Change-Id: I16f20956a1490da02acc24156360aef235111494 Signed-off-by: Michał Kopeć <[email protected]>
Change-Id: I2e05a6f76308b8b89ec9279888ae9fc6a80152a0 Signed-off-by: Michał Kopeć <[email protected]>
Change-Id: I4c6655eda6729f2c12f99a09174da6ebc2795258 Signed-off-by: Michał Kopeć <[email protected]>
Change-Id: If7b6108379828a9032c38417a4b4dc2204c87356 Signed-off-by: Michał Kopeć <[email protected]>
Change-Id: I820044e39d161c5c993d2cd6bb51bcb56eb9e9ba Signed-off-by: Michał Kopeć <[email protected]>
Add Clevo V5x0TU mainboard. Preliminary support for the dGPU variant (V5x0TNx) is also added, but full support will be added in subsequent patches. Change-Id: Ic4ffba29e50b6bf2ee010d798f7a952d1264f15c Signed-off-by: Michał Kopeć <[email protected]> Co-authored-by: Michał Żygowski <[email protected]> Co-authored-by: Filip Gołaś <[email protected]>
The submodules are updated in subsequent steps anyway. Change-Id: I4243ae3862c89306d355c9559708b22cb86f4d44 Signed-off-by: Michał Kopeć <[email protected]>
Set the L1 substate optimize register to 0xF, like Insyde does. I don't know what exactly that does, but it works :D Change-Id: I833e2478cccff4c7f711f1b0614c5fcb6513aafa Signed-off-by: Michał Kopeć <[email protected]>
Change-Id: I39529022821f96bfee6aaaee9cc86072c90393a2 Signed-off-by: Michał Kopeć <[email protected]>
Silences a warning from fwupd when booting with EDK2 payload. Change-Id: I9c7e1f76c1833476b0f88e5a40e888a1721eb1b3 Signed-off-by: Michał Kopeć <[email protected]>
…dorcode Change-Id: If7203621e7767bae8ad791947e61e5aefb31bc19 Signed-off-by: Michał Kopeć <[email protected]>
…older Change-Id: I780f662d5df516cc46fa6b4ac180e8cbb1c8c8e8 Signed-off-by: Michał Kopeć <[email protected]>
Change-Id: I56f3cfdeb2bfc4f07e4595009fa89acbf048da92 Signed-off-by: Michał Kopeć <[email protected]>
The CSE MKHI_BUP_COMMON_GET_BOOT_PERF_DATA command is also implemented in non-Lite CSE SKUs. TEST=Boot NovaCustom V540TU (MTL-P / ME Consumer) with SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V2 selected and check `cbmem -t`: 990:CSME ROM started execution 0 944:CSE sent 'Boot Stall Done' to PMC 34,000 945:CSE started to handle ICC configuration 172,000 (138,000) 946:CSE sent 'Host BIOS Prep Done' to PMC 172,000 (0) 947:CSE received 'CPU Reset Done Ack sent' from PMC 314,000 (142,000) 991:Die Management Unit (DMU) load completed 360,000 (46,000) 0:1st timestamp 385,844 (25,844) 11:start of bootblock 398,796 (12,952) 12:end of bootblock 402,099 (3,302) [...] Change-Id: I3a5b1abd282af9af33cef2371719df4133684a2e Signed-off-by: Michał Kopeć <[email protected]>
DDR5 uses a Serial Presence Detect (SPD) with hub function (SPD5 hub device) to store the SPD data. The SPD5 hub has 1024 bytes of EEPROM (`CONFIG_DIMM_SPD_SIZE=1024`). Change-Id: Ic5e6c58f255bef86b68ce90a4f853bf4e7c7ccfe Co-authored-by: Meera Ravindranath <[email protected]> Signed-off-by: Jeremy Soller <[email protected]> Signed-off-by: Tim Crawford <[email protected]>
Apply CB:75284 to Meteor Lake. CB:52731 introduced support for reading SPD from the EEPROM via SMBus. Replace the now unneeded workaround for DDR5 with filling in the correct channels for DDR5. Change-Id: I600d8fd480cb84d5dcb679e4f0bdeeaaebfab386 Signed-off-by: Jeremy Soller <[email protected]> Signed-off-by: Tim Crawford <[email protected]>
Change-Id: Ibc4e00dec9953a426d8dacf87f3a09c57a80d9e6 Signed-off-by: Michał Kopeć <[email protected]>
CSE will not respond to EOP in Debug mode. Change-Id: Ifba407c52c6384ca7932ce353b1a66d4da3f6661 Signed-off-by: Michał Kopeć <[email protected]>
Intel introduced a new UPD specifically for setting the HDA subsystem ID in FSP-M. Using SiSsidTablePtr in FSP-S no longer works as it will be locked with a default value of 0 by that point. Tested on Clevo V560TU with MTL FSP 4122.12 (0D.00.A8.20). TEST=PCI config space for HDA device has subsystem ID set. Change-Id: I5e668747d99b955b0a3946524c5918d328b8e1d3 Signed-off-by: Tim Crawford <[email protected]>
This patch refactors RAMTOP MTRR type selection to address a critical NEM logic bug on SoCs with non-power-of-two cache sets. This bug can cause runtime hangs when Write Back (WB) caching is enabled. Workaround: Force MTRR type to WC (Write Combining) on affected SoCs when the cache set count is not a power of two. BUG=b:306677879 BRANCH=firmware-rex-15709.B TEST=Verified boot on google/ovis and google/rex (including Ovis with non-power-of-two cache configuration). Change-Id: Ia9a8f0d37d581b05c19ea7f9b1a07933caa956d4 Signed-off-by: Subrata Banik <[email protected]> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81269 Reviewed-by: Stefan Reinauer <[email protected]> Tested-by: build bot (Jenkins) <[email protected]>
Introduce a function to determine whether the number of cache sets is a power of two. This aligns with common cache design practices that favor power-of-two counts for efficient indexing and addressing. BUG=b:306677879 BRANCH=firmware-rex-15709.B TEST=Verified functionality on google/ovis and google/rex (including a non-power-of-two Ovis configuration). Change-Id: I819e0d1aeb4c1dbe1cdf3115b2e172588a6e8da5 Signed-off-by: Subrata Banik <[email protected]> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81268 Reviewed-by: Stefan Reinauer <[email protected]> Tested-by: build bot (Jenkins) <[email protected]>
This patch enables the `SOC_INTEL_COMMON_BASECODE_RAMTOP` configuration at the SoC level for all MTL devices. This change streamlines the configuration process, avoiding redundant selections on individual mainboards. BUG=b:306677879 BRANCH=firmware-rex-15709.B TEST=Verified boot functionality on google/ovis and google/rex. Change-Id: I3aa3a83c190d0a0e93c267222a9dca0ac7651f9c Signed-off-by: Subrata Banik <[email protected]> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81271 Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: Stefan Reinauer <[email protected]>
Change-Id: I702013a6532534bf4fffa824bfd8e4a550abdd3a Signed-off-by: Michał Kopeć <[email protected]>
Change-Id: Ia3c6a35e5b37fb1a33cbf69c177b37298e04321e Signed-off-by: Michał Żygowski <[email protected]>
Caching the RAMTOP causes issues with FSP MemoryInit for platforms with DIMM modules. When memories are swapped, the training may sometimes hang randomly. Seems to be a manifestation of the issue described here: https://review.coreboot.org/c/coreboot/+/81269/ (despite the L3 cache sets is power of 2 on the tested i5-1235U SKU). Disabling the RAMTOP caching make the memory training reliable no matter how many times the DIMM modules are swapped/changed in slots. RAMTOP was designed primarily for boot time optimizations in mind (most likely for Chromebooks), so disable the RAMTOP caching for all non-ChromeOS builds to boot reliably. Signed-off-by: Michał Żygowski <[email protected]>
This is a workaround for modules that don't correctly populate the serial number field in SPD. When such modules are swapped, they generate the same CRC, causing FSP to mistakenly consider them the same, and attempt to restore cached MRC settings. This won't work when the modules are different. As a workaround, force retrain the memory when RTC failure is detected. Users are expected to reset their CMOS upon changing memory modules. Change-Id: Iebb2810914b728317ce5ebd84b61667d2ba10529 Signed-off-by: Michał Kopeć <[email protected]>
Doesn't work with any FSP revs tested so far. Change-Id: Ifd112230cdfc645e68f2146677008b200ae1b0a3 Signed-off-by: Michał Kopeć <[email protected]>
Change-Id: Iae4bb0965aee8dad819320570b1852939a6ecab7 Signed-off-by: Michał Kopeć <[email protected]>
Change-Id: I4843ed215bff8a003799b399885950e69d1daf4d Signed-off-by: Michał Kopeć <[email protected]>
Change-Id: I16517f3b76cf706650adafbe38af1d280b4d2f3d Signed-off-by: Michał Kopeć <[email protected]>
Signed-off-by: Michał Żygowski <[email protected]>
…le lines Rationale: coreboot coding style guidelines Signed-off-by: Michał Kopeć <[email protected]>
Signed-off-by: Michał Kopeć <[email protected]>
Signed-off-by: Michał Kopeć <[email protected]>
Signed-off-by: Michał Kopeć <[email protected]>
Rename to page_ptr which more closely aligns with the SPD5 spec. Signed-off-by: Michał Kopeć <[email protected]>
Reduce amount of nested if statements by adding separate branches for DDR5, DDR4 and older SPD variants. Signed-off-by: Michał Kopeć <[email protected]>
DDR5 SPD page length is 1024 bytes. Signed-off-by: Michał Kopeć <[email protected]>
Signed-off-by: Filip Gołaś <[email protected]>
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