MP4: Pipelined RV32I Processor

Workflow for Running the Processor

1. Update cache parameters defined in apply_cache_params.sh
   
   Recommended high-performance settings (despite being area-hungry) are

NSET1=4
NWAY1=2
NSET2=7
NWAY2=2
WORDSIZE=8
MULTILV_I_CACHE=0
MULTILV_D_CACHE=1

2. Compile SRAM using OpenRAM
   
   This script uses pkg/_types_pt2 to track the latest parameters to determine if recompilation is necessary.
   If the script misbehaves, manually delete pkg/_types_pt2 to force a rebuild.

$ ./apply_cache_params.sh

3. Lint design using Synopsys SpyGlass

$ cd lint
$ make lint
$ cd ..

4. Compile design using Synopsys VCS

$ make sim/top_tb

5. Run simulation on CoreMark and check for errors using Spike (RISC-V ISA Simulator)

$ make run_top_tb PROG=testcode/competition/coremark_rv32i.elf
$ make spike ELF=testcode/competition/coremark_rv32i.elf
$ diff sim/spike.log sim/golden_spike.log

6. Synthesize design using Synopsys Design Compiler

$ cd synth
$ make synth