MP4: Pipelined RV32I Processor

Workflow for Running the Processor

1. Update cache parameters defined in apply_cache_params.sh
   
   Recommended high-performance settings (despite being area-hungry) are

NSET1=4
NWAY1=2
NSET2=7
NWAY2=2
WORDSIZE=8
MULTILV_I_CACHE=0
MULTILV_D_CACHE=1

2. Compile SRAM using OpenRAM
   
   This script uses pkg/_types_pt2 to track the latest parameters to determine if recompilation is necessary.
   If the script misbehaves, manually delete pkg/_types_pt2 to force a rebuild.

$ ./apply_cache_params.sh

3. Lint design using Synopsys SpyGlass

$ cd lint
$ make lint
$ cd ..

4. Compile design using Synopsys VCS

$ make sim/top_tb

5. Run simulation on CoreMark and check for errors using Spike (RISC-V ISA Simulator)

$ make run_top_tb PROG=testcode/competition/coremark_rv32i.elf
$ make spike ELF=testcode/competition/coremark_rv32i.elf
$ diff sim/spike.log sim/golden_spike.log

6. Synthesize design using Synopsys Design Compiler

$ cd synth
$ make synth

MP3: Unified 4-Way SA Cache

Workflow for Running the Design

1. Compile design using Synopsys VCS and run DUT unit test
   
   TEST CASES ARE NOT IMPLEMENTED

$ make run_cache_dut

2. Run full simulation and check for errors using Spike

$ make run_top_tb PROG=memio.s
$ make spike ELF=memio.s
$ diff sim/spike.log sim/golden_spike.log

3. Synthesize design using Synopsys Design Compiler

$ cd synth
$ make synth

MP2: The RV32I Processor

Workflow for Running the Design

1. Compile design using Synopsys VCS, run simulation, and check for errors using Spike

$ make run PROG=testcode/riscv_mp2test.s
$ make spike ELF=testcode/riscv_mp2test.s
$ diff sim/spike.log sim/golden_spike.log

2. Inspect the simulation trace using Synopsys Verdi
   
   RUN VERDI ONLY IN REMOTE EWS DESKTOP UNLESS LOCAL X-FORWARDING IS CORRECTLY SET UP

$ ./run_verdi.sh

3. Synthesize design using Synopsys Design Compiler

$ cd synth
$ make synth

MP1: SystemVerilog HDL and HVL

$ make run
$ make grade

Resources

/
├── class
│   └── ece411
│       ├── freepdk-45nm
│       ├── gem5
│       ├── OpenRAM
│       ├── opt
│       ├── software
│       ├── testbed
│       └── ece411.sh
└── software
    ├── ews
    ├── gcc-12.3.0
    ├── lc3tools-12
    └── llvm-15.0.7

MP0: Environment Setup

1. Set up SSH with X-forwarding

Host ece411
  HostName linux.ews.illinois.edu
  ForwardX11 yes
  ForwardX11Trusted yes
  ForwardAgent yes
  Compression yes
  User NETID

2. Create an SSH key and link it to GitHub

$ ssh-keygen -t ed25519
$ eval "$(ssh-agent -s)"
$ ssh-add ~/.ssh/id_ed25519
$ cat ~/.ssh/id_ed25519.pub

3. Clone repository and merge release

$ git init
$ git remote add origin [email protected]:illinois-cs-coursework/fa23_ece411_NETID.git
$ git remote add release [email protected]:illinois-cs-coursework/fa23_ece411_.release.git
$ git pull origin main
$ git branch -m main
$ git fetch release
$ git merge --allow-unrelated-histories release/mp0 -m "Merging provided MP0 files"
$ git push --set-upstream origin main

4. Set up and test Synopsys software

$ echo 'source /class/ece411/ece411.sh' >> ~/.bashrc
$ make run
$ ./run_verdi.sh
$ make synth