Skip to content
View zhengzhideakang's full-sized avatar
2 followers · 0 following

Block or report zhengzhideakang

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Popular repositories Loading

  1. Verilog--FIFO Verilog--FIFO Public

    包含同步FIFO，异步FIFO，不同位宽转换

    Verilog 5

  2. Verilog--moving-average Verilog--moving-average Public

    Verilog功能模块——滑动平均值（使用FIFO）

    Verilog 1

  3. Verilog--I2C Verilog--I2C Public

    verilog-function-module--I2C-master-slave

    Verilog 1

  4. Verilog--Uart Verilog--Uart Public

    串口通信模块

    Verilog

  5. Verilog--Key Verilog--Key Public

    Verilog按键消抖

    Verilog

  6. Verilog--clkDivider Verilog--clkDivider Public

    Verilog功能模块——时钟分频，任意整数分频

    Verilog