boards: avnet: add avnet zuboard 1cg #90920
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Hello @singular0770, and thank you very much for your first pull request to the Zephyr project! |
| CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=100000000 | ||
| CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000 |
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should be set in soc Kconfig using dts functions
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You think this should be set in the ZynqMP SOC defconfig (soc/xlnx/zynqmp/Kconfig.soc)? I'd like to keep scope of this PR to just this board as there's a lot of work going on from AMD right now to better support their platform. Last time the ZynqMP value changed was 35ca8c9 where it was significantly slowed down for the QEMU R5.
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there should be a dts device that specifies the cycles per second, and that should be read/set by the soc Kconfig.defconfig file, the ticks per second can be set there too. Neither should be set in a board defconfig file
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Can you take a look now? I updated the ZynqMP Kconfig.defconfig to use dt_node_int_prop_int to retrieve the clock-frequency parameter of the selected triple-timer counter as CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC.
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Add board definition for the Avnet ZUBoarcd 1CG development board. This board is based on the Zynq Ultrascale+ MPSoC. As with other boards based on this platform, currently only the first R5 core is supported. Signed-off-by: Michael Estes <[email protected]>
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Adds initial support for the Avnet ZUBoard 1CG based on the AMD Zynq Ultrascale+ MPSoC. As with other boards in this family, support is currently limited to the first Cortex-R5 and does not support the Cortex A53 cores, second cortex R5, or dual core lockstep on the R5s. This board port is based on the AMD Kria KV260 starter kit, with the deviation that a new sram1 region is defined which matches the rproc_0_reserved memory region in the zynqmp_openamp.dtsi file in Linux so more memory is available to Zephyr than just the ATCM and the app can be run via remoteproc from Linux.