soc/intel_adsp: add support for Intel Jasper Lake

Add a variant of Intel cAVS2.0 used in Jasper Lake based
products.

Signed-off-by: Kai Vehmanen <[email protected]>

boards/xtensa/intel_adsp_cavs20/Kconfig.board

@@ -1,8 +1,12 @@
 # Xtensa board configuration
 
-# Copyright (c) 2020 Intel Corporation
+# Copyright (c) 2020,2022 Intel Corporation
 # SPDX-License-Identifier: Apache-2.0
 
 config  BOARD_INTEL_ADSP_CAVS20
-	bool "Intel ADSP CAVS 2.0"
+	bool "Intel ADSP CAVS 2.0 for Ice Lake"
+	depends on SOC_SERIES_INTEL_CAVS_V20
+
+config  BOARD_INTEL_ADSP_CAVS20_JSL
+	bool "Intel ADSP CAVS 2.0 for Jasper Lake"
 	depends on SOC_SERIES_INTEL_CAVS_V20

boards/xtensa/intel_adsp_cavs20/Kconfig.defconfig

@@ -1,11 +1,12 @@
-# Copyright (c) 2020 Intel Corporation
+# Copyright (c) 2020,2022 Intel Corporation
 #
 # SPDX-License-Identifier: Apache-2.0
 
-if BOARD_INTEL_ADSP_CAVS20
+if BOARD_INTEL_ADSP_CAVS20 || BOARD_INTEL_ADSP_CAVS20_JSL
 
 config BOARD
-	default "intel_adsp_cavs20"
+	default "intel_adsp_cavs20" if BOARD_INTEL_ADSP_CAVS20
+	default "intel_adsp_cavs20_jsl" if BOARD_INTEL_ADSP_CAVS20_JSL
 
 config CAVS_ICTL_0_OFFSET
 	default 6
@@ -35,4 +36,4 @@ config 2ND_LVL_ISR_TBL_OFFSET
 config CAVS_ISR_TBL_OFFSET
 	default 2ND_LVL_ISR_TBL_OFFSET
 
-endif # BOARD_INTEL_ADSP_CAVS20
+endif # BOARD_INTEL_ADSP_CAVS20 || BOARD_INTEL_ADSP_CAVS20_JSL

boards/xtensa/intel_adsp_cavs20/board.cmake

@@ -3,4 +3,10 @@
 board_set_flasher_ifnset(misc-flasher)
 board_finalize_runner_args(misc-flasher)
 
+if(CONFIG_BOARD_INTEL_ADSP_CAVS20)
 board_set_rimage_target(icl)
+endif()
+
+if(CONFIG_BOARD_INTEL_ADSP_CAVS20_JSL)
+board_set_rimage_target(jsl)
+endif()

boards/xtensa/intel_adsp_cavs20/intel_adsp_cavs20_jsl.dts

@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2020 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <intel/intel_cavs20_jsl.dtsi>
+
+/ {
+	model = "intel_adsp_cavs20_jsl";
+	compatible = "intel";
+
+	chosen {
+		zephyr,sram = &sram0;
+	};
+};

boards/xtensa/intel_adsp_cavs20/intel_adsp_cavs20_jsl.yaml

@@ -0,0 +1,11 @@
+identifier: intel_adsp_cavs20_jsl
+name: cAVS 2.0 Audio DSP for Intel Jasper Lake (converged Audio Voice and Speech)
+type: mcu
+arch: xtensa
+toolchain:
+  - xcc
+  - zephyr
+testing:
+  ignore_tags:
+     - net
+     - bluetooth

boards/xtensa/intel_adsp_cavs20/intel_adsp_cavs20_jsl_defconfig

@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_MAIN_STACK_SIZE=2048
+
+CONFIG_SOC_SERIES_INTEL_CAVS_V20=y
+CONFIG_BOARD_INTEL_ADSP_CAVS20_JSL=y
+
+CONFIG_GEN_ISR_TABLES=y
+CONFIG_GEN_IRQ_VECTOR_TABLE=n
+
+CONFIG_XTENSA_RESET_VECTOR=y
+
+CONFIG_XTENSA_USE_CORE_CRT1=y
+
+CONFIG_MULTI_LEVEL_INTERRUPTS=y
+CONFIG_2ND_LEVEL_INTERRUPTS=y
+CONFIG_CAVS_ICTL=y
+
+CONFIG_BOOTLOADER_SRAM_SIZE=192
+CONFIG_BUILD_OUTPUT_BIN=n
+CONFIG_CLEANUP_INTERMEDIATE_FILES=y

dts/xtensa/intel/intel_cavs20_jsl.dtsi

@@ -0,0 +1,120 @@
+/*
+ * Copyright (c) 2019 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <xtensa/intel/intel_cavs.dtsi>
+#include <mem.h>
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "cdns,tensilica-xtensa-lx4";
+			reg = <0>;
+		};
+
+		cpu1: cpu@1 {
+			device_type = "cpu";
+			compatible = "cdns,tensilica-xtensa-lx4";
+			reg = <1>;
+		};
+
+	};
+
+	sram0: memory@be000000 {
+		device_type = "memory";
+		compatible = "mmio-sram";
+		reg = <0xbe000000 DT_SIZE_K(1024)>;
+	};
+
+	sram1: memory@be800000 {
+		device_type = "memory";
+		compatible = "mmio-sram";
+		reg = <0xbe800000 DT_SIZE_K(64)>;
+	};
+
+	soc {
+		shim: shim@71f00 {
+			compatible = "intel,cavs-shim";
+			reg = <0x71f00 0x100>;
+		};
+
+		win: win@71a00 {
+			compatible = "intel,cavs-win";
+			reg = <0x71a00 0x20>;
+		};
+
+		l2lm: l2lm@71d00 {
+			compatible = "intel,cavs-l2lm";
+			reg = <0x71d00 0x20>;
+		};
+
+		core_intc: core_intc@0 {
+			compatible = "cdns,xtensa-core-intc";
+			reg = <0x00 0x400>;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+		};
+
+		cavs_host_ipc: cavs_host_ipc@71e00 {
+			compatible = "intel,cavs-host-ipc";
+			reg = <0x71e00 0x30>;
+			interrupts = <7 0 0>;
+			interrupt-parent = <&cavs0>;
+		};
+
+		cavs0: cavs@78800  {
+			compatible = "intel,cavs-intc";
+			reg = <0x78800 0x10>;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			interrupts = <6 0 0>;
+			interrupt-parent = <&core_intc>;
+			label = "CAVS_0";
+		};
+
+		cavs1: cavs@78810  {
+			compatible = "intel,cavs-intc";
+			reg = <0x78810 0x10>;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			interrupts = <0xA 0 0>;
+			interrupt-parent = <&core_intc>;
+			label = "CAVS_1";
+		};
+
+		cavs2: cavs@78820  {
+			compatible = "intel,cavs-intc";
+			reg = <0x78820 0x10>;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			interrupts = <0XD 0 0>;
+			interrupt-parent = <&core_intc>;
+			label = "CAVS_2";
+		};
+
+		cavs3: cavs@78830  {
+			compatible = "intel,cavs-intc";
+			reg = <0x78830 0x10>;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			interrupts = <0x10 0 0>;
+			interrupt-parent = <&core_intc>;
+			label = "CAVS_3";
+		};
+
+		idc: idc@1200 {
+			compatible = "intel,cavs-idc";
+			label = "CAVS_IDC";
+			reg = <0x1200 0x80>;
+			interrupts = <8 0 0>;
+			interrupt-parent = <&cavs0>;
+		};
+
+	};
+};

samples/subsys/audio/sof/boards/intel_adsp_cavs20_jsl.conf

@@ -0,0 +1,5 @@
+CONFIG_ICELAKE=y
+CONFIG_INTEL_DMIC=y
+CONFIG_INTEL_SSP=y
+CONFIG_LP_MEMORY_BANKS=1
+CONFIG_HP_MEMORY_BANKS=16

soc/xtensa/intel_adsp/common/boot.c

@@ -45,7 +45,11 @@
 #elif defined(CONFIG_SOC_SERIES_INTEL_CAVS_V20)
 #define PLATFORM_INIT_HPSRAM
 #define PLATFORM_INIT_LPSRAM
+#if defined(CONFIG_BOARD_INTEL_ADSP_CAVS20_JSL)
+#define PLATFORM_HPSRAM_EBB_COUNT 16
+#else
 #define PLATFORM_HPSRAM_EBB_COUNT 47
+#endif
 #define EBB_SEGMENT_SIZE          32
 
 #elif defined(CONFIG_SOC_SERIES_INTEL_CAVS_V18)