Skip to content

Commit

Permalink
don't output nested generate/endgenerate regions
Browse files Browse the repository at this point in the history
  • Loading branch information
zachjs committed Aug 1, 2023
1 parent fb2f300 commit 0102e4a
Show file tree
Hide file tree
Showing 3 changed files with 10 additions and 2 deletions.
4 changes: 2 additions & 2 deletions src/Language/SystemVerilog/AST/GenItem.hs
Original file line number Diff line number Diff line change
Expand Up @@ -17,7 +17,7 @@ import Language.SystemVerilog.AST.ShowHelp
import Language.SystemVerilog.AST.Expr (Expr)
import Language.SystemVerilog.AST.Op (AsgnOp)
import Language.SystemVerilog.AST.Type (Identifier)
import {-# SOURCE #-} Language.SystemVerilog.AST.ModuleItem (ModuleItem)
import {-# SOURCE #-} Language.SystemVerilog.AST.ModuleItem (ModuleItem, showGenModuleItem)

data GenItem
= GenBlock Identifier [GenItem]
Expand Down Expand Up @@ -45,7 +45,7 @@ instance Show GenItem where
x2 (show o2) (show e2)
(showBlockedBranch s) -- Verilog 2001 requires this to be a block
show (GenNull) = ""
show (GenModuleItem item) = show item
show (GenModuleItem item) = showGenModuleItem item

showBareBlock :: GenItem -> String
showBareBlock (GenBlock x i) =
Expand Down
5 changes: 5 additions & 0 deletions src/Language/SystemVerilog/AST/ModuleItem.hs
Original file line number Diff line number Diff line change
Expand Up @@ -16,6 +16,7 @@ module Language.SystemVerilog.AST.ModuleItem
, AssignOption (..)
, Severity (..)
, AssertionItem (..)
, showGenModuleItem
) where

import Data.List (intercalate)
Expand Down Expand Up @@ -96,6 +97,10 @@ showModportDecl (dir, ident, e) =
then printf "%s %s" (show dir) ident
else printf "%s .%s(%s)" (show dir) ident (show e)

showGenModuleItem :: ModuleItem -> String
showGenModuleItem (Generate genItems) = show genItems
showGenModuleItem item = show item

type PortBinding = (Identifier, Expr)

type ModportDecl = (Direction, Identifier, Expr)
Expand Down
3 changes: 3 additions & 0 deletions src/Language/SystemVerilog/AST/ModuleItem.hs-boot
Original file line number Diff line number Diff line change
@@ -1,7 +1,10 @@
module Language.SystemVerilog.AST.ModuleItem
( ModuleItem
, showGenModuleItem
) where

data ModuleItem
instance Eq ModuleItem
instance Show ModuleItem

showGenModuleItem :: ModuleItem -> String

0 comments on commit 0102e4a

Please sign in to comment.