Notes_Peak_Detector

Some study notes for Digital Design's Assignment 2.

Name		Name	Last commit message	Last commit date
Latest commit History 7 Commits
2023_02_15.docx		2023_02_15.docx
BYTE_PRINTING.pdf		BYTE_PRINTING.pdf
BYTE_PRINTING.png		BYTE_PRINTING.png
Behavioural Modelling in VHDL.pdf		Behavioural Modelling in VHDL.pdf
Command新图.pdf		Command新图.pdf
Command老图.pdf		Command老图.pdf
Digital Synchronous System Design.pdf		Digital Synchronous System Design.pdf
ECHO.pdf		ECHO.pdf
ECHO.png		ECHO.png
Introduction to VHDL.pdf		Introduction to VHDL.pdf
Modelling Sequential Logic in VHDL.pdf		Modelling Sequential Logic in VHDL.pdf
README.md		README.md
VHDL Timing Model.pdf		VHDL Timing Model.pdf
VHDL中的行为建模.pdf		VHDL中的行为建模.pdf
VHDL时序模型.pdf		VHDL时序模型.pdf
VHDL简介.pdf		VHDL简介.pdf
command_processor.txt		command_processor.txt
data_design.txt		data_design.txt
data_processor.txt		data_processor.txt
topArch_A2.docx		topArch_A2.docx
topArch_A2.pdf		topArch_A2.pdf
在VHDL中建模时序逻辑.pdf		在VHDL中建模时序逻辑.pdf
数字同步系统设计.pdf		数字同步系统设计.pdf

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