Releases: ymherklotz/verismith
Releases · ymherklotz/verismith
Verismith 0.6.0.2
v0.6.0.2
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ymherklotz
Yann Herklotz
5fbfc3f
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ymherklotz
Yann Herklotz
Changelog
- Add back correct clean function in reduction step.
Verismith 0.6.0.1
v0.6.0.1
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ymherklotz
Yann Herklotz
091e0b3
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ymherklotz
Yann Herklotz
Changelog
- Add configuration to set default yosys version (
default.yosys). - Add documentation for all the configuration options.
Verismith 0.6.0.0
v0.6.0.0
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ymherklotz
Yann Herklotz
b6ac3e9
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ymherklotz
Yann Herklotz
v0.6.0.0 Verismith 0.6.0.0
Verismith 0.5.0.1
4d962a7
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ymherklotz
Yann Herklotz
v0.5.0.1 Move to resources
FPGA '20 Artifact Evaluation
4d962a7
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ymherklotz
Yann Herklotz
fpga20 Move to resources
Verismith 0.5.0.0
Changelog
Bug fixes
- Mask the output of simulator based on golden design #58.
- Update dependency for Hedgehog #63.
- Error in for loop reduction #64.
- Fix parser with new modules #65.
Features
- Added support for Quartus and Quartus light.
- Added flags to control fuzz run.
- Added flags to rerun fuzz run with custom Verilog.
Verismith 0.4.0.1
- Fix generation of module instances with missing connections.
Verismith 0.4.0.0
b787507
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ymherklotz
Yann Herklotz
- Reproducible builds and newest dependencies.
Verismith 0.3.1.0
5bbf138
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ymherklotz
Yann Herklotz
- Add proper generation of modules
- Add nix build instead of stack
Verismith 0.3.0.0
a9f1887
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ymherklotz
Yann Herklotz
- Add report backend and new fuzz loop