Abhishek Balakrishnan Yaqi Zhang
The goal of our project is to implement error correcting circuitry in a standard 5-stage pipelined processor in order to operate at higher frequencies without compromising power and guaranteeing the correct result. This project seeks to replicate the results of the Resilient Power-Tuning Schemes proposed by Intel’s Architecture Group. While this group factored in temperature and voltage conditions into the dynamic events that cause errors, we are only looking at how to detect and overcome the errors and performance losses that are induced by overclocking in conventional pipelined processors.