feat: updating from newer svd2rust

build.rs

@@ -1,3 +1,4 @@
+#![doc = r" Builder file for Peripheral access crate generated by svd2rust tool"]
 use std::env;
 use std::fs::File;
 use std::io::Write;

src/can.rs

@@ -1,69 +1,121 @@
 #[doc = r"Register block"]
 #[repr(C)]
 pub struct RegisterBlock {
-    #[doc = "0x00 - CAN Clock Control Register"]
-    pub clc: CLC,
+    clc: CLC,
     _reserved1: [u8; 0x04],
+    id: ID,
+    fdr: FDR,
+    _reserved3: [u8; 0xf0],
+    list: [LIST; 8],
+    _reserved4: [u8; 0x20],
+    mspnd: [MSPND; 8],
+    _reserved5: [u8; 0x20],
+    msid: [MSID; 8],
+    _reserved6: [u8; 0x20],
+    msimask: MSIMASK,
+    panctr: PANCTR,
+    mcr: MCR,
+    mitr: MITR,
+}
+impl RegisterBlock {
+    #[doc = "0x00 - CAN Clock Control Register"]
+    #[inline(always)]
+    pub const fn clc(&self) -> &CLC {
+        &self.clc
+    }
     #[doc = "0x08 - Module Identification Register"]
-    pub id: ID,
+    #[inline(always)]
+    pub const fn id(&self) -> &ID {
+        &self.id
+    }
     #[doc = "0x0c - CAN Fractional Divider Register"]
-    pub fdr: FDR,
-    _reserved3: [u8; 0xf0],
+    #[inline(always)]
+    pub const fn fdr(&self) -> &FDR {
+        &self.fdr
+    }
     #[doc = "0x100..0x120 - List Register"]
-    pub list: [LIST; 8],
-    _reserved4: [u8; 0x20],
+    #[inline(always)]
+    pub const fn list(&self, n: usize) -> &LIST {
+        &self.list[n]
+    }
     #[doc = "0x140..0x160 - Message Pending Register"]
-    pub mspnd: [MSPND; 8],
-    _reserved5: [u8; 0x20],
+    #[inline(always)]
+    pub const fn mspnd(&self, n: usize) -> &MSPND {
+        &self.mspnd[n]
+    }
     #[doc = "0x180..0x1a0 - Message Index Register"]
-    pub msid: [MSID; 8],
-    _reserved6: [u8; 0x20],
+    #[inline(always)]
+    pub const fn msid(&self, n: usize) -> &MSID {
+        &self.msid[n]
+    }
     #[doc = "0x1c0 - Message Index Mask Register"]
-    pub msimask: MSIMASK,
+    #[inline(always)]
+    pub const fn msimask(&self) -> &MSIMASK {
+        &self.msimask
+    }
     #[doc = "0x1c4 - Panel Control Register"]
-    pub panctr: PANCTR,
+    #[inline(always)]
+    pub const fn panctr(&self) -> &PANCTR {
+        &self.panctr
+    }
     #[doc = "0x1c8 - Module Control Register"]
-    pub mcr: MCR,
+    #[inline(always)]
+    pub const fn mcr(&self) -> &MCR {
+        &self.mcr
+    }
     #[doc = "0x1cc - Module Interrupt Trigger Register"]
-    pub mitr: MITR,
+    #[inline(always)]
+    pub const fn mitr(&self) -> &MITR {
+        &self.mitr
+    }
 }
-#[doc = "CLC (rw) register accessor: an alias for `Reg<CLC_SPEC>`"]
+#[doc = "CLC (rw) register accessor: CAN Clock Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clc::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clc`]
+module"]
 pub type CLC = crate::Reg<clc::CLC_SPEC>;
 #[doc = "CAN Clock Control Register"]
 pub mod clc;
-#[doc = "ID (r) register accessor: an alias for `Reg<ID_SPEC>`"]
+#[doc = "ID (r) register accessor: Module Identification Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id`]
+module"]
 pub type ID = crate::Reg<id::ID_SPEC>;
 #[doc = "Module Identification Register"]
 pub mod id;
-#[doc = "FDR (rw) register accessor: an alias for `Reg<FDR_SPEC>`"]
+#[doc = "FDR (rw) register accessor: CAN Fractional Divider Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fdr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fdr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fdr`]
+module"]
 pub type FDR = crate::Reg<fdr::FDR_SPEC>;
 #[doc = "CAN Fractional Divider Register"]
 pub mod fdr;
-#[doc = "LIST (r) register accessor: an alias for `Reg<LIST_SPEC>`"]
+#[doc = "LIST (r) register accessor: List Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`list::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@list`]
+module"]
 pub type LIST = crate::Reg<list::LIST_SPEC>;
 #[doc = "List Register"]
 pub mod list;
-#[doc = "MSPND (rw) register accessor: an alias for `Reg<MSPND_SPEC>`"]
+#[doc = "MSPND (rw) register accessor: Message Pending Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mspnd::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mspnd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mspnd`]
+module"]
 pub type MSPND = crate::Reg<mspnd::MSPND_SPEC>;
 #[doc = "Message Pending Register"]
 pub mod mspnd;
-#[doc = "MSID (r) register accessor: an alias for `Reg<MSID_SPEC>`"]
+#[doc = "MSID (r) register accessor: Message Index Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msid::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@msid`]
+module"]
 pub type MSID = crate::Reg<msid::MSID_SPEC>;
 #[doc = "Message Index Register"]
 pub mod msid;
-#[doc = "MSIMASK (rw) register accessor: an alias for `Reg<MSIMASK_SPEC>`"]
+#[doc = "MSIMASK (rw) register accessor: Message Index Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msimask::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`msimask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@msimask`]
+module"]
 pub type MSIMASK = crate::Reg<msimask::MSIMASK_SPEC>;
 #[doc = "Message Index Mask Register"]
 pub mod msimask;
-#[doc = "PANCTR (rw) register accessor: an alias for `Reg<PANCTR_SPEC>`"]
+#[doc = "PANCTR (rw) register accessor: Panel Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`panctr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`panctr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@panctr`]
+module"]
 pub type PANCTR = crate::Reg<panctr::PANCTR_SPEC>;
 #[doc = "Panel Control Register"]
 pub mod panctr;
-#[doc = "MCR (rw) register accessor: an alias for `Reg<MCR_SPEC>`"]
+#[doc = "MCR (rw) register accessor: Module Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mcr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mcr`]
+module"]
 pub type MCR = crate::Reg<mcr::MCR_SPEC>;
 #[doc = "Module Control Register"]
 pub mod mcr;
-#[doc = "MITR (w) register accessor: an alias for `Reg<MITR_SPEC>`"]
+#[doc = "MITR (w) register accessor: Module Interrupt Trigger Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mitr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mitr`]
+module"]
 pub type MITR = crate::Reg<mitr::MITR_SPEC>;
 #[doc = "Module Interrupt Trigger Register"]
 pub mod mitr;

src/can/clc.rs

@@ -1,51 +1,19 @@
 #[doc = "Register `CLC` reader"]
-pub struct R(crate::R<CLC_SPEC>);
-impl core::ops::Deref for R {
-    type Target = crate::R<CLC_SPEC>;
-    #[inline(always)]
-    fn deref(&self) -> &Self::Target {
-        &self.0
-    }
-}
-impl From<crate::R<CLC_SPEC>> for R {
-    #[inline(always)]
-    fn from(reader: crate::R<CLC_SPEC>) -> Self {
-        R(reader)
-    }
-}
+pub type R = crate::R<CLC_SPEC>;
 #[doc = "Register `CLC` writer"]
-pub struct W(crate::W<CLC_SPEC>);
-impl core::ops::Deref for W {
-    type Target = crate::W<CLC_SPEC>;
-    #[inline(always)]
-    fn deref(&self) -> &Self::Target {
-        &self.0
-    }
-}
-impl core::ops::DerefMut for W {
-    #[inline(always)]
-    fn deref_mut(&mut self) -> &mut Self::Target {
-        &mut self.0
-    }
-}
-impl From<crate::W<CLC_SPEC>> for W {
-    #[inline(always)]
-    fn from(writer: crate::W<CLC_SPEC>) -> Self {
-        W(writer)
-    }
-}
+pub type W = crate::W<CLC_SPEC>;
 #[doc = "Field `DISR` reader - Module Disable Request Bit"]
-pub type DISR_R = crate::BitReader<bool>;
+pub type DISR_R = crate::BitReader;
 #[doc = "Field `DISR` writer - Module Disable Request Bit"]
-pub type DISR_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLC_SPEC, bool, O>;
+pub type DISR_W<'a, REG> = crate::BitWriter<'a, REG>;
 #[doc = "Field `DISS` reader - Module Disable Status Bit"]
-pub type DISS_R = crate::BitReader<bool>;
+pub type DISS_R = crate::BitReader;
 #[doc = "Field `EDIS` reader - Sleep Mode Enable Control"]
-pub type EDIS_R = crate::BitReader<bool>;
+pub type EDIS_R = crate::BitReader;
 #[doc = "Field `EDIS` writer - Sleep Mode Enable Control"]
-pub type EDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLC_SPEC, bool, O>;
+pub type EDIS_W<'a, REG> = crate::BitWriter<'a, REG>;
 #[doc = "Field `SBWE` writer - Module Suspend Bit Write Enable for OCDS"]
-pub type SBWE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLC_SPEC, bool, O>;
+pub type SBWE_W<'a, REG> = crate::BitWriter<'a, REG>;
 impl R {
     #[doc = "Bit 0 - Module Disable Request Bit"]
     #[inline(always)]
@@ -67,40 +35,41 @@ impl W {
     #[doc = "Bit 0 - Module Disable Request Bit"]
     #[inline(always)]
     #[must_use]
-    pub fn disr(&mut self) -> DISR_W<0> {
-        DISR_W::new(self)
+    pub fn disr(&mut self) -> DISR_W<CLC_SPEC> {
+        DISR_W::new(self, 0)
     }
     #[doc = "Bit 3 - Sleep Mode Enable Control"]
     #[inline(always)]
     #[must_use]
-    pub fn edis(&mut self) -> EDIS_W<3> {
-        EDIS_W::new(self)
+    pub fn edis(&mut self) -> EDIS_W<CLC_SPEC> {
+        EDIS_W::new(self, 3)
     }
     #[doc = "Bit 4 - Module Suspend Bit Write Enable for OCDS"]
     #[inline(always)]
     #[must_use]
-    pub fn sbwe(&mut self) -> SBWE_W<4> {
-        SBWE_W::new(self)
+    pub fn sbwe(&mut self) -> SBWE_W<CLC_SPEC> {
+        SBWE_W::new(self, 4)
     }
-    #[doc = "Writes raw bits to the register."]
+    #[doc = r" Writes raw bits to the register."]
+    #[doc = r""]
+    #[doc = r" # Safety"]
+    #[doc = r""]
+    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
     #[inline(always)]
     pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
-        self.0.bits(bits);
+        self.bits = bits;
         self
     }
 }
-#[doc = "CAN Clock Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clc](index.html) module"]
+#[doc = "CAN Clock Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clc::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CLC_SPEC;
 impl crate::RegisterSpec for CLC_SPEC {
     type Ux = u32;
 }
-#[doc = "`read()` method returns [clc::R](R) reader structure"]
-impl crate::Readable for CLC_SPEC {
-    type Reader = R;
-}
-#[doc = "`write(|w| ..)` method takes [clc::W](W) writer structure"]
+#[doc = "`read()` method returns [`clc::R`](R) reader structure"]
+impl crate::Readable for CLC_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`clc::W`](W) writer structure"]
 impl crate::Writable for CLC_SPEC {
-    type Writer = W;
     const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
     const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
 }