[top_englishbreakfast] Remove pin dedicated for UART debugging

Signed-off-by: Pirmin Vogel <[email protected]>
vogelpi · Sep 19, 2024 · c938040 · c938040
1 parent b2cee40
commit c938040
Show file tree

Hide file tree

Showing 3 changed files with 1 addition and 15 deletions.
diff --git a/hw/top_englishbreakfast/data/pins_cw305.xdc b/hw/top_englishbreakfast/data/pins_cw305.xdc
@@ -55,9 +55,7 @@ set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { IO_USB_D
 set_property -dict { PACKAGE_PIN D16 IOSTANDARD LVCMOS33 } [get_ports { IO_USB_SENSE0 }]; #JP3.D16
 set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { IO_USB_DNPULLUP0 }]; #JP3.E16
 
-set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { IO_UTX_DEBUG }]; #JP3.G16 (UART) for debugging
-
-## Unused pins of JP3: B12, F12
+## Unused pins of JP3: B12, F12, G16
 
 ## 20-Pin Connector (JP1)
 

diff --git a/hw/top_englishbreakfast/data/top_englishbreakfast.hjson b/hw/top_englishbreakfast/data/top_englishbreakfast.hjson
@@ -900,7 +900,6 @@
           // ChipWhisperer IO
           { name: 'IO_CLKOUT',        type: 'BidirStd', bank: 'VCC', connection: 'manual', desc: 'Manual clock output for SCA setup'}
           { name: 'IO_TRIGGER',       type: 'BidirStd', bank: 'VCC', connection: 'manual', desc: 'Manual trigger output for SCA setup'}
-          { name: 'IO_UTX_DEBUG',     type: 'BidirStd', bank: 'VCC', connection: 'manual', desc: 'Manual UART TX debug output'}
         ],
       }
 

diff --git a/util/topgen/templates/chiplevel.sv.tpl b/util/topgen/templates/chiplevel.sv.tpl
@@ -1291,11 +1291,7 @@ module chip_${top["name"]}_${target["name"]} #(
   // 20-pin connector. This is used for SCA/FI experiments only.
 
   logic unused_inputs;
-  % if target["name"] == "cw305":
-  assign unused_inputs = manual_in_io_clkout ^ manual_in_io_trigger ^ manual_in_io_utx_debug;
-  % else:
   assign unused_inputs = manual_in_io_clkout ^ manual_in_io_trigger;
-  % endif
 
   // Synchronous clock output to capture board.
   assign manual_out_io_clkout = manual_in_io_clk;
@@ -1372,12 +1368,5 @@ module chip_${top["name"]}_${target["name"]} #(
       manual_in_io_clk_trigger_sw_en | (manual_in_io_clk_trigger_hw_en &
           prim_mubi_pkg::mubi4_test_false_strict(manual_in_io_clk_idle));
 % endif
-## This separate UART debugging output is needed for the CW305 only.
-% if target["name"] == "cw305":
-
-  // UART Tx for debugging. The UART itself is connected to the capture board.
-  assign manual_out_io_utx_debug = top_${top["name"]}.cio_uart0_tx_d2p;
-  assign manual_oe_io_utx_debug = 1'b1;
-% endif
 
 endmodule : chip_${top["name"]}_${target["name"]}