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[pinmux/dif] Document WARL semantics of pad attribute registers
The MIO|DIO_PAD_ATTR registers are specified as WARL meaning certain bits written by software may get discarded by the hardware. For example the supported number of drive strength bits can depend on the hardware platform (simulation, FPGA, silicon). When configuring pad attributes, the DIF performs a readback of the written value and signals an error if they don't match. This commit doesn't alter the behavior of the DIF but it documents the behavior and in particular the expection that higher-level software needs to decide on how to resolve the situation. This is related to lowRISC#24577. Signed-off-by: Pirmin Vogel <[email protected]>
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