[aes, pre-dv] Pre-dv Verilator testbench for AES

This commit contains a comprehensive pre-dv testbench for the AES IP
block, invoking all the possible modes of operations (+GCM) with
different key and inputs sizes. By default, the communication with the
IP happens over the TLUL bus, but if a TLUL/shim adapter is
configured, messages can be relayed through the shim first.

There are two generic modules `tlul_adapter` and `tlul_delayer` that
are agnostic to the actual testbench and can be reused in other
testbenches that require a robust TLUL handler.

This testbench mimics already existing pre-dv suites for Ascon and
KMAC.

Signed-off-by: Andrea Caforio <[email protected]>

hw/ip/aes/pre_dv/aes_tb/README.md

@@ -0,0 +1,58 @@
+# TLUL/Shim Verilator Testbench
+
+This directory contains the Verilator testbench for the AES IP block.
+Out of the box, the testbench contains test vectors for most of the salient use cases, nonetheless extending the testbench with further tests is straightforward as detailed below.
+By default, communication with the IP happens over the TLUL bus.
+If a TLUL/shim adapter is available, messages can optionally be relayed by the shim.
+
+## Current Test Vectors
+
+The `./data` directory contains an array of `.svh` files each of them containing a single set of input stimuli that constitute a test:
+
+```
+data
+├── gcm_k128_a0_d0.svh    # AES-GCM-128 Encryption; 0 AD Bytes; 0 Msg Bytes
+├── gcm_k128_a0_d16.svh   # AES-GCM-128 Encryption; 0 AD Bytes; 16 Msg Bytes
+├── gcm_k128_a20_d60.svh  # AES-GCM-128 Encryption/Decryption/Save/Restore; 20 AD Bytes; 60 Msg Bytes
+├── gcm_k128_a20_d64.svh  # AES-GCM-128 Encryption; 20 AD Bytes; 64 Msg Bytes
+└── modes_d64.svh         # AES-{128,192,256}-{ECB,CBC,OFB,CFB,CTR} Encryption/Decryption
+```
+
+### Adding/Modifying Tests
+
+Each test vector file `./data/*.svh` starts with a preamble that instruments both the testbench RTL as well as the `c_dpi` model:
+
+```systemverilog
+`define AD_LENGTH    // Number of AD bytes
+`define MSG_LENGTH   // Number of Msg bytes
+`define NUM_REQUESTS // Total number of requests
+```
+
+Here, `NUM_REQUESTS` denotes the number of `read_request`, `write_request` and `c_dpi_load` invocations within the file.
+Having written a new test vector file, the `fusesoc` configuration needs to be made aware of it.
+
+1. Add the `.svh` filename to the list of RTL files under `files_rtl/files`.
+2. Add the `.svh` filename to the `DREQUESTS_FILE` Verilator variable under `verilator/verilator_options`.
+
+## Building and Running the Verilator Testbench
+
+To build the testbench, execute from the OpenTitan top level:
+
+```sh
+fusesoc --cores-root=. --verbose run --setup --build lowrisc:dv_verilator:aes_tb
+```
+To execute the obtained Verilator binary and with trace generation, run:
+
+```sh
+./build/lowrisc_dv_verilator_aes_tb_0/default-verilator/Vaes_tb --trace
+```
+
+## Details of the testbench
+
+- cpp/aes\_tb.cc: contains main function and instantiation of SimCtrl
+- rtl/aes\_tb.sv: contains the testbench logic
+- rtl/tlul\_delayer.sv: contains an optional delayer module to artificially induce random delays in the TLUL bus.
+- rtl/tlul\_adapter_tb_reqs.sv: is an adapter than converts generic read/write requests into TLUL requests.
+- rtl/aes\_tb_reqs.sv: contains requests (stimuli) that are fed to the testbench.
+- rtl/aes\_tb_pkg.sv: contains common parameters and functions.
+- data/*: contains test vector files.

hw/ip/aes/pre_dv/aes_tlul_shim_tb/aes_tlul_shim_tb.core → hw/ip/aes/pre_dv/aes_tb/aes_tb.core

@@ -2,8 +2,8 @@ CAPI=2:
 # Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
-name: "lowrisc:dv_verilator:aes_tlul_shim_tb"
-description: "AES TLUL Shim TB"
+name: "lowrisc:dv_verilator:aes_tb"
+description: "AES TB"
 filesets:
   files_rtl:
     depend:
@@ -16,19 +16,20 @@ filesets:
       - data/gcm_k128_a0_d16.svh : {is_include_file : true}
       - data/gcm_k128_a0_d0.svh : {is_include_file : true}
       - data/modes_d64.svh : {is_include_file : true}
-      - rtl/aes_tlul_shim_tb_pkg.sv
-      - rtl/aes_tlul_shim_tb_reqs.sv
-      - rtl/aes_tlul_shim_tb_c_dpi.sv
-      - rtl/aes_tlul_shim_delayer.sv
-      - rtl/aes_tlul_shim_tb.sv
+      - rtl/aes_tb_pkg.sv
+      - rtl/aes_tb_reqs.sv
+      - rtl/aes_tb_c_dpi.sv
+      - rtl/tlul_delayer.sv
+      - rtl/tlul_adapter_tb_reqs.sv
+      - rtl/aes_tb.sv
     file_type: systemVerilogSource
 
   files_dv_verilator:
     depend:
       - lowrisc:dv_verilator:simutil_verilator
 
     files:
-      - cpp/aes_tlul_shim_tb.cc
+      - cpp/aes_tb.cc
     file_type: cppSource
 
 targets:
@@ -37,7 +38,7 @@ targets:
     filesets:
       - files_rtl
       - files_dv_verilator
-    toplevel: aes_tlul_shim_tb
+    toplevel: aes_tb
     tools:
       verilator:
         mode: cc
@@ -55,7 +56,7 @@ targets:
 # -O
 #   Optimization levels have a large impact on the runtime performance of the
 #   simulation model. -O2 and -O3 are pretty similar, -Os is slower than -O2/-O3
-          - '-CFLAGS "-std=c++11 -Wall -DVM_TRACE_FMT_FST -DTOPLEVEL_NAME=aes_tlul_shim_tb -g -O0"'
+          - '-CFLAGS "-std=c++11 -Wall -DVM_TRACE_FMT_FST -DTOPLEVEL_NAME=aes_tb -g -O0"'
           - '-LDFLAGS "-pthread -lutil -lelf"'
           - "-Wall"
           # XXX: Cleanup all warnings and remove this option

hw/ip/aes/pre_dv/aes_tlul_shim_tb/cpp/aes_tlul_shim_tb.cc → hw/ip/aes/pre_dv/aes_tb/cpp/aes_tb.cc

@@ -6,30 +6,29 @@
 #include <iostream>
 #include <signal.h>
 
-#include "Vaes_tlul_shim_tb.h"
+#include "Vaes_tb.h"
 #include "sim_ctrl_extension.h"
 #include "verilated_toplevel.h"
 #include "verilator_sim_ctrl.h"
 
-class AesTlulShimTb : public SimCtrlExtension {
+class AesTb : public SimCtrlExtension {
   using SimCtrlExtension::SimCtrlExtension;
 
  public:
-  AesTlulShimTb(aes_tlul_shim_tb *top);
+  AesTb(aes_tb *top);
 
   void OnClock(unsigned long sim_time);
 
  private:
-  aes_tlul_shim_tb *top_;
+  aes_tb *top_;
 };
 
 // Constructor:
 // - Set up top_ ptr
-AesTlulShimTb::AesTlulShimTb(aes_tlul_shim_tb *top)
-    : SimCtrlExtension{}, top_(top) {}
+AesTb::AesTb(aes_tb *top) : SimCtrlExtension{}, top_(top) {}
 
 // Function called once every clock cycle from SimCtrl
-void AesTlulShimTb::OnClock(unsigned long sim_time) {
+void AesTb::OnClock(unsigned long sim_time) {
   if (top_->test_done_o) {
     VerilatorSimCtrl::GetInstance().RequestStop(top_->test_passed_o);
   }
@@ -39,18 +38,18 @@ int main(int argc, char **argv) {
   int ret_code;
 
   // Init verilog instance
-  aes_tlul_shim_tb top;
+  aes_tb top;
 
   // Init sim
   VerilatorSimCtrl &simctrl = VerilatorSimCtrl::GetInstance();
   simctrl.SetTop(&top, &top.clk_i, &top.rst_ni,
                  VerilatorSimCtrlFlags::ResetPolarityNegative);
 
   // Create and register VerilatorSimCtrl extension
-  AesTlulShimTb aes_tlul_shim_tb(&top);
-  simctrl.RegisterExtension(&aes_tlul_shim_tb);
+  AesTb aes_tb(&top);
+  simctrl.RegisterExtension(&aes_tb);
 
-  std::cout << "Simulation of AES TLUL Shim" << std::endl
+  std::cout << "Simulation of AES Testbench" << std::endl
             << "=============================" << std::endl
             << std::endl;
 

hw/ip/aes/pre_dv/aes_tlul_shim_tb/data/gcm_k128_a0_d0.svh → hw/ip/aes/pre_dv/aes_tb/data/gcm_k128_a0_d0.svh

@@ -10,7 +10,7 @@
 `define DATA_LENGTH 0
 `define NUM_REQUESTS 42
 
-`define REQUESTS shim_request_t requests[`NUM_REQUESTS] = '{                                        \
+`define REQUESTS bus_request_t requests[`NUM_REQUESTS] = '{                                         \
   c_dpi_load('{                                                                                     \
       operation:  AES_ENC,                                                                          \
       mode:       AES_GCM,                                                                          \

hw/ip/aes/pre_dv/aes_tlul_shim_tb/data/gcm_k128_a0_d16.svh → hw/ip/aes/pre_dv/aes_tb/data/gcm_k128_a0_d16.svh

@@ -10,7 +10,7 @@
 `define DATA_LENGTH 16
 `define NUM_REQUESTS 55
 
-`define REQUESTS shim_request_t requests[`NUM_REQUESTS] = '{                                        \
+`define REQUESTS bus_request_t requests[`NUM_REQUESTS] = '{                                         \
   c_dpi_load('{                                                                                     \
       operation:  AES_ENC,                                                                          \
       mode:       AES_GCM,                                                                          \

hw/ip/aes/pre_dv/aes_tlul_shim_tb/data/gcm_k128_a20_d60.svh → hw/ip/aes/pre_dv/aes_tb/data/gcm_k128_a20_d60.svh

@@ -10,7 +10,7 @@
 `define DATA_LENGTH 60
 `define NUM_REQUESTS 370
 
-`define REQUESTS shim_request_t requests[`NUM_REQUESTS] = '{                                        \
+`define REQUESTS bus_request_t requests[`NUM_REQUESTS] = '{                                         \
                                                                                                     \
   /*****************************************************************************/                   \
   /** AES-GCM-128 Encryption                                                  **/                   \

hw/ip/aes/pre_dv/aes_tlul_shim_tb/data/gcm_k128_a20_d64.svh → hw/ip/aes/pre_dv/aes_tb/data/gcm_k128_a20_d64.svh

@@ -10,7 +10,7 @@
 `define DATA_LENGTH 64
 `define NUM_REQUESTS 110
 
-`define REQUESTS shim_request_t requests[`NUM_REQUESTS] = '{                                        \
+`define REQUESTS bus_request_t requests[`NUM_REQUESTS] = '{                                         \
   c_dpi_load('{                                                                                     \
       operation:  AES_ENC,                                                                          \
       mode:       AES_GCM,                                                                          \

hw/ip/aes/pre_dv/aes_tlul_shim_tb/data/modes_d64.svh → hw/ip/aes/pre_dv/aes_tb/data/modes_d64.svh

@@ -10,7 +10,7 @@
 `define DATA_LENGTH 64
 `define NUM_REQUESTS 1982
 
-`define REQUESTS shim_request_t requests[`NUM_REQUESTS] = '{                                        \
+`define REQUESTS bus_request_t requests[`NUM_REQUESTS] = '{                                         \
                                                                                                     \
   /*****************************************************************************/                   \
   /** AES-ECB-128 Encryption                                                  **/                   \