Reading coil data bits is reversed

Fixes brainelectronics#38
vladimir1284 · Sep 2, 2023 · d9f6a5e · d9f6a5e
1 parent e9ab05a
commit d9f6a5e
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diff --git a/.gitignore b/.gitignore
@@ -155,3 +155,4 @@ dmypy.json
 
 # Cython debug symbols
 cython_debug/
+.vscode/settings.json
diff --git a/umodbus/modbus.py b/umodbus/modbus.py
@@ -33,6 +33,7 @@ class Modbus(object):
     :param      addr_list:  List of addresses
     :type       addr_list:  List[int]
     """
+
     def __init__(self, itf, addr_list: List[int]) -> None:
         self._itf = itf
         self._addr_list = addr_list
@@ -167,6 +168,13 @@ def _create_response(self,
         # 05    0000 0101
         #
         # 1011 0011   1101 0110   1010 0000
+        # Fixing issue #38 from @robertonaranjo
+        n = len(data)
+        fp = data[:8]
+        lp = data[8:n]
+        fp.reverse()
+        lp.reverse()
+        data = fp + lp
 
         return data
Original file line number	Diff line number	Diff line change
Expand Up		@@ -155,3 +155,4 @@ dmypy.json

		# Cython debug symbols
		cython_debug/
		.vscode/settings.json