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@vinitkesh
vinitkesh committed Jun 6, 2024
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1 change: 1 addition & 0 deletions docs/.vitepress/config.mjs
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Expand Up @@ -5,6 +5,7 @@ export default defineConfig({
title: "Hardware Lab NITC",
description: "An official hardware lab wesbsite",
head: [['link', { rel: 'icon', href: '/img/favicon.ico' }]],
base: '/hwlabnitc.github.io/',
themeConfig: {
outline: { level: 'deep' },
// https://vitepress.dev/reference/default-theme-config
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4 changes: 2 additions & 2 deletions docs/.vitepress/dist/404.html
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Expand Up @@ -8,15 +8,15 @@
<meta name="generator" content="VitePress v1.2.3">
<link rel="preload stylesheet" href="/assets/style.CTsPrQqq.css" as="style">

<script type="module" src="/assets/app.LVOefQDj.js"></script>
<script type="module" src="/assets/app.BVAsbgWq.js"></script>
<link rel="preload" href="/assets/inter-roman-latin.Di8DUHzh.woff2" as="font" type="font/woff2" crossorigin="">
<link rel="icon" href="/img/favicon.ico">
<script id="check-dark-mode">(()=>{const e=localStorage.getItem("vitepress-theme-appearance")||"auto",a=window.matchMedia("(prefers-color-scheme: dark)").matches;(!e||e==="auto"?a:e==="dark")&&document.documentElement.classList.add("dark")})();</script>
<script id="check-mac-os">document.documentElement.classList.toggle("mac",/Mac|iPhone|iPod|iPad/i.test(navigator.platform));</script>
</head>
<body>
<div id="app"></div>
<script>window.__VP_HASH_MAP__=JSON.parse("{\"mips_index.md\":\"CY43yMpU\",\"index.md\":\"C96AY5Xz\",\"verilog_main.md\":\"yPPbu8m8\",\"about.md\":\"CY5iuE6T\",\"verilog_index.md\":\"BmIHPG-w\",\"mips_main.md\":\"B6bGXt9J\",\"verilog_intro_readme.md\":\"CnTl2NNp\",\"verilog_singlecycle.md\":\"DvYIvDh1\"}");window.__VP_SITE_DATA__=JSON.parse("{\"lang\":\"en-US\",\"dir\":\"ltr\",\"title\":\"Hardware Lab NITC\",\"description\":\"An official hardware lab wesbsite\",\"base\":\"/\",\"head\":[],\"router\":{\"prefetchLinks\":true},\"appearance\":true,\"themeConfig\":{\"outline\":{\"level\":\"deep\"},\"nav\":[{\"text\":\"Home\",\"link\":\"/\"},{\"text\":\"Verilog Guide\",\"link\":\"/Verilog/\"},{\"text\":\"MIPS Guide\",\"link\":\"/MIPS/\"}],\"search\":{\"provider\":\"local\"},\"sidebar\":[{\"text\":\"Examples\",\"items\":[{\"text\":\"Verilog\",\"link\":\"/markdown-examples\"},{\"text\":\"MIPS\",\"link\":\"/api-examples\"}]}],\"socialLinks\":[{\"icon\":\"github\",\"link\":\"https://github.com/vuejs/vitepress\"}],\"footer\":{\"copyright\":\"Copyright © 2024 National Institute of Technology Calicut\"}},\"locales\":{},\"scrollOffset\":134,\"cleanUrls\":false}");</script>
<script>window.__VP_HASH_MAP__=JSON.parse("{\"mips_index.md\":\"CY43yMpU\",\"verilog_main.md\":\"yPPbu8m8\",\"mips_main.md\":\"B6bGXt9J\",\"about.md\":\"CY5iuE6T\",\"index.md\":\"Ccl4vJqT\",\"verilog_index.md\":\"BmIHPG-w\",\"verilog_intro_readme.md\":\"CnTl2NNp\",\"verilog_singlecycle.md\":\"DvYIvDh1\"}");window.__VP_SITE_DATA__=JSON.parse("{\"lang\":\"en-US\",\"dir\":\"ltr\",\"title\":\"Hardware Lab NITC\",\"description\":\"An official hardware lab wesbsite\",\"base\":\"/\",\"head\":[],\"router\":{\"prefetchLinks\":true},\"appearance\":true,\"themeConfig\":{\"outline\":{\"level\":\"deep\"},\"nav\":[{\"text\":\"Home\",\"link\":\"/\"},{\"text\":\"Verilog Guide\",\"link\":\"/Verilog/\"},{\"text\":\"MIPS Guide\",\"link\":\"/MIPS/\"}],\"search\":{\"provider\":\"local\"},\"sidebar\":[{\"text\":\"Examples\",\"items\":[{\"text\":\"Verilog\",\"link\":\"/markdown-examples\"},{\"text\":\"MIPS\",\"link\":\"/api-examples\"}]}],\"socialLinks\":[{\"icon\":\"github\",\"link\":\"https://github.com/vuejs/vitepress\"}],\"footer\":{\"copyright\":\"Copyright © 2024 National Institute of Technology Calicut\"}},\"locales\":{},\"scrollOffset\":134,\"cleanUrls\":false}");</script>

</body>
</html>
6 changes: 3 additions & 3 deletions docs/.vitepress/dist/MIPS/index.html
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6 changes: 3 additions & 3 deletions docs/.vitepress/dist/Verilog/Intro/README.html
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6 changes: 3 additions & 3 deletions docs/.vitepress/dist/Verilog/SingleCycle.html
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Expand Up @@ -8,10 +8,10 @@
<meta name="generator" content="VitePress v1.2.3">
<link rel="preload stylesheet" href="/assets/style.CTsPrQqq.css" as="style">

<script type="module" src="/assets/app.LVOefQDj.js"></script>
<script type="module" src="/assets/app.BVAsbgWq.js"></script>
<link rel="preload" href="/assets/inter-roman-latin.Di8DUHzh.woff2" as="font" type="font/woff2" crossorigin="">
<link rel="modulepreload" href="/assets/chunks/framework.CgMb17D3.js">
<link rel="modulepreload" href="/assets/chunks/theme.Cy6MXi6G.js">
<link rel="modulepreload" href="/assets/chunks/theme.B6pbfA9S.js">
<link rel="modulepreload" href="/assets/Verilog_SingleCycle.md.DvYIvDh1.lean.js">
<link rel="icon" href="/img/favicon.ico">
<script id="check-dark-mode">(()=>{const e=localStorage.getItem("vitepress-theme-appearance")||"auto",a=window.matchMedia("(prefers-color-scheme: dark)").matches;(!e||e==="auto"?a:e==="dark")&&document.documentElement.classList.add("dark")})();</script>
Expand Down Expand Up @@ -438,7 +438,7 @@
<span class="line"><span style="--shiki-light:#24292E;--shiki-dark:#E1E4E8;"> end </span></span>
<span class="line"><span style="--shiki-light:#24292E;--shiki-dark:#E1E4E8;"> end </span></span>
<span class="line"><span style="--shiki-light:#24292E;--shiki-dark:#E1E4E8;">endmodule</span></span></code></pre></div><h2 id="_8-references" tabindex="-1">8. References <a class="header-anchor" href="#_8-references" aria-label="Permalink to &quot;8. References&quot;">​</a></h2><ul><li>&quot;Computer Organization and Design: The Hardware/Software Interface&quot; by David Patterson and John Hennessy</li><li>“Digital design and Computer architecture” by David Money Harris &amp; Sarah L. Harris.</li><li>“Digital Logic and Computer Design ”by M. Morris Mano.</li><li>“Verilog HDL: A Guide to Digital Design and Synthesis ” by Samir Palnitkar.</li></ul></div></div></main><footer class="VPDocFooter" data-v-39a288b8 data-v-d4a0bba5><!--[--><!--]--><!----><nav class="prev-next" aria-labelledby="doc-footer-aria-label" data-v-d4a0bba5><span class="visually-hidden" id="doc-footer-aria-label" data-v-d4a0bba5>Pager</span><div class="pager" data-v-d4a0bba5><!----></div><div class="pager" data-v-d4a0bba5><a class="VPLink link pager-link next" href="/markdown-examples.html" data-v-d4a0bba5><!--[--><span class="desc" data-v-d4a0bba5>Next page</span><span class="title" data-v-d4a0bba5>Verilog</span><!--]--></a></div></nav></footer><!--[--><!--]--></div></div></div><!--[--><!--]--></div></div><footer class="VPFooter has-sidebar" data-v-5d98c3a5 data-v-e315a0ad><div class="container" data-v-e315a0ad><!----><p class="copyright" data-v-e315a0ad>Copyright © 2024 National Institute of Technology Calicut</p></div></footer><!--[--><!--]--></div></div>
<script>window.__VP_HASH_MAP__=JSON.parse("{\"mips_index.md\":\"CY43yMpU\",\"index.md\":\"C96AY5Xz\",\"verilog_main.md\":\"yPPbu8m8\",\"about.md\":\"CY5iuE6T\",\"verilog_index.md\":\"BmIHPG-w\",\"mips_main.md\":\"B6bGXt9J\",\"verilog_intro_readme.md\":\"CnTl2NNp\",\"verilog_singlecycle.md\":\"DvYIvDh1\"}");window.__VP_SITE_DATA__=JSON.parse("{\"lang\":\"en-US\",\"dir\":\"ltr\",\"title\":\"Hardware Lab NITC\",\"description\":\"An official hardware lab wesbsite\",\"base\":\"/\",\"head\":[],\"router\":{\"prefetchLinks\":true},\"appearance\":true,\"themeConfig\":{\"outline\":{\"level\":\"deep\"},\"nav\":[{\"text\":\"Home\",\"link\":\"/\"},{\"text\":\"Verilog Guide\",\"link\":\"/Verilog/\"},{\"text\":\"MIPS Guide\",\"link\":\"/MIPS/\"}],\"search\":{\"provider\":\"local\"},\"sidebar\":[{\"text\":\"Examples\",\"items\":[{\"text\":\"Verilog\",\"link\":\"/markdown-examples\"},{\"text\":\"MIPS\",\"link\":\"/api-examples\"}]}],\"socialLinks\":[{\"icon\":\"github\",\"link\":\"https://github.com/vuejs/vitepress\"}],\"footer\":{\"copyright\":\"Copyright © 2024 National Institute of Technology Calicut\"}},\"locales\":{},\"scrollOffset\":134,\"cleanUrls\":false}");</script>
<script>window.__VP_HASH_MAP__=JSON.parse("{\"mips_index.md\":\"CY43yMpU\",\"verilog_main.md\":\"yPPbu8m8\",\"mips_main.md\":\"B6bGXt9J\",\"about.md\":\"CY5iuE6T\",\"index.md\":\"Ccl4vJqT\",\"verilog_index.md\":\"BmIHPG-w\",\"verilog_intro_readme.md\":\"CnTl2NNp\",\"verilog_singlecycle.md\":\"DvYIvDh1\"}");window.__VP_SITE_DATA__=JSON.parse("{\"lang\":\"en-US\",\"dir\":\"ltr\",\"title\":\"Hardware Lab NITC\",\"description\":\"An official hardware lab wesbsite\",\"base\":\"/\",\"head\":[],\"router\":{\"prefetchLinks\":true},\"appearance\":true,\"themeConfig\":{\"outline\":{\"level\":\"deep\"},\"nav\":[{\"text\":\"Home\",\"link\":\"/\"},{\"text\":\"Verilog Guide\",\"link\":\"/Verilog/\"},{\"text\":\"MIPS Guide\",\"link\":\"/MIPS/\"}],\"search\":{\"provider\":\"local\"},\"sidebar\":[{\"text\":\"Examples\",\"items\":[{\"text\":\"Verilog\",\"link\":\"/markdown-examples\"},{\"text\":\"MIPS\",\"link\":\"/api-examples\"}]}],\"socialLinks\":[{\"icon\":\"github\",\"link\":\"https://github.com/vuejs/vitepress\"}],\"footer\":{\"copyright\":\"Copyright © 2024 National Institute of Technology Calicut\"}},\"locales\":{},\"scrollOffset\":134,\"cleanUrls\":false}");</script>

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