Parmys doc (#47)

* cleaned

* make format-py

* write arch cleaned

* yosys -> parmys

* doc update started

* ODIN_II -> odin_ii

* odin_ii refactored

* task/flow figures updated

* doc updated

* sv test issue

Author: poname

README.md

@@ -6,7 +6,7 @@
 The Verilog-to-Routing (VTR) project is a world-wide collaborative effort to provide an open-source framework for conducting FPGA architecture and CAD research and development.
 The VTR design flow takes as input a Verilog description of a digital circuit, and a description of the target FPGA architecture.
 It then performs:
-  * Elaboration & Synthesis (ODIN II)
+  * Elaboration, Synthesis & Partial Mapping (PARMYS)
   * Logic Optimization & Technology Mapping (ABC)
   * Packing, Placement, Routing & Timing Analysis (VPR)
 

doc/src/vtr/Makefile

@@ -6,7 +6,7 @@ TEX_OPTS := -file-line-error -halt-on-error -interaction=errorstopmode -shell-es
 # -use-make tells latexmk to call make for generating missing files.
 LATEXMK_OPTS := -pdf -pdflatex="$(TEX) $(TEX_OPTS)" -recorder -use-make
 
-FIG_TARGETS := vtr_flow_fig.pdf vtr_flow_fig.svg
+FIG_TARGETS := vtr_flow_fig.pdf vtr_flow_fig.svg vtr_task_fig.pdf vtr_task_fig.svg
 
 .PHONY: clean distclean
 

doc/src/vtr/cad_flow.rst

@@ -9,7 +9,7 @@ VTR CAD Flow
 
     VTR CAD flow (and variants)
 
-In the standard VTR Flow (:numref:`fig_vtr_cad_flow`), :ref:`odin_ii` converts a Verilog Hardware Destription Language (HDL) design into a flattened netlist consisting of logic gates, flip-flops, and blackboxes representing heterogeneous blocks (e.g. adders, multipliers, RAM slices) :cite:`jamieson_odin_II`.
+In the standard VTR Flow (:numref:`fig_vtr_cad_flow`), :ref:`parmys` converts a Verilog Hardware Destription Language (HDL) design into a flattened netlist consisting of logic gates, flip-flops, and blackboxes representing heterogeneous blocks (e.g. adders, multipliers, RAM slices).
 
 Next, the :ref:`abc`  synthesis package is used to perform technology-independent logic optimization, and technology-maps the circuit into LUTs :cite:`abc_cite,pistorius_benchmarking_method_fpga_synthesis,cho_priority_cuts`.
 The output of ABC is a :ref:`.blif format <blif_format>` netlist of LUTs, flip flops, and blackboxes.

doc/src/vtr/parse_config.rst

@@ -17,7 +17,7 @@ Each line contains a semicolon delimited tuple in the following format::
 
     This name is used when generating the output files of :ref:`parse_vtr_task` and :ref:`parse_vtr_flow`.
 
-* ``<file_to_search_within>``: The name of the file that will be searched (vpr.out, odin.out, etc.)
+* ``<file_to_search_within>``: The name of the file that will be searched (vpr.out, parmys.out, etc.)
 
 * ``<regex>``: A perl regular expression used to find the desired value.
 

doc/src/vtr/parse_vtr_flow.rst

@@ -21,7 +21,7 @@ Typical usage is::
 
 where:
 
-  * ``<parse_path>`` is the directory path that contains the files to be parsed (e.g. ``vpr.out``, ``odin.out``, etc).
+  * ``<parse_path>`` is the directory path that contains the files to be parsed (e.g. ``vpr.out``, ``parmys.out``, etc).
   * ``<parse_config_file>`` is the path to the :ref:`vtr_parse_config` file.
 
 Output

doc/src/vtr/run_vtr_flow.rst

@@ -74,7 +74,7 @@ The parser for these runs is considered the Yosys conventional Verilog/SystemVer
 .. code-block:: bash
 
     # Using the Yosys-SystemVerilog plugin if installed, otherwise the Yosys conventional Verilog parser
-    ./run_vtr_flow <path/to/SystemVerilog/File> <path/to/arch/file> -start yosys -parser yosys-plugin
+    ./run_vtr_flow <path/to/SystemVerilog/File> <path/to/arch/file> -parser system-verilog
 
     # Using the Surelog plugin if installed, otherwise failure on the unsupported file type
     ./run_vtr_flow <path/to/UHDM/File> <path/to/arch/file> -start yosys -parser surelog
@@ -186,23 +186,23 @@ Detailed Command-line Options
 
 .. option:: -min_hard_mult_size <int>
 
-    Tells ODIN II the minimum multiplier size that should be implemented
+    Tells Parmys/ODIN II the minimum multiplier size that should be implemented
     using hard multiplier (if available). Smaller multipliers will be
     implemented using soft logic.
 
     **Default:** 3
 
 .. option:: -min_hard_adder_size <int>
 
-    Tells ODIN II the minimum adder size that should be implemented
+    Tells Parmys/ODIN II the minimum adder size that should be implemented
     using hard adders (if available). Smaller adders will be
     implemented using soft logic.
 
     **Default:** 1
 
 .. option:: -adder_cin_global
 
-    Tells ODIN II to connect the first cin in an adder/subtractor chain
+    Tells Parmys/ODIN II to connect the first cin in an adder/subtractor chain
     to a global gnd/vdd net. Instead of creating a dummy adder to generate
     the input signal of the first cin port of the chain.
 
@@ -222,13 +222,13 @@ Detailed Command-line Options
 
 .. option:: -min_hard_mult_size <min_hard_mult_size>
 
-    Tells ODIN II the minimum multiplier size (in bits) to be implemented using hard multiplier.
+    Tells Parmys/ODIN II the minimum multiplier size (in bits) to be implemented using hard multiplier.
 
     **Default:** 3
 
 .. option:: -min_hard_adder_size <MIN_HARD_ADDER_SIZE>
 
-    Tells ODIN II the minimum adder size (in bits) that should be implemented using hard adder.
+    Tells Parmys/ODIN II the minimum adder size (in bits) that should be implemented using hard adder.
 
     **Default:** 1
 
@@ -238,7 +238,7 @@ Detailed Command-line Options
 
 .. option:: -yosys_script <YOSYS_SCRIPT>
 
-    Supplies Yosys with a .ys script file (similar to Tcl script), including the synthesis steps.
+    Supplies Parmys(Yosys) with a .ys script file (similar to Tcl script), including the synthesis steps.
 
     **Default:** None
 

doc/src/vtr/running_vtr.rst

@@ -7,7 +7,7 @@ VTR is a collection of tools that perform the full FPGA CAD flow from Verilog to
 
 The design flow consists of:
 
-* :ref:`odin_ii` (Logic Synthesis)
+* :ref:`parmys` (Logic Synthesis & Partial Mapping)
 * :ref:`abc` (Logic Optimization & Technology Mapping)
 * :ref:`vpr` (Pack, Place & Route)