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@verilog-to-routing

Verilog to Routing

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  1. vtr-verilog-to-routing Public

    Verilog to Routing -- Open Source CAD Flow for FPGA Research

    C++ 1.1k 408

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Showing 7 of 7 repositories
  • vtr-verilog-to-routing Public

    Verilog to Routing -- Open Source CAD Flow for FPGA Research

    C++ 1,078 408 446 (15 issues need help) 54 Updated Apr 17, 2025
  • verilog-to-routing.github.io Public

    Website for Verilog to Routing

    SCSS 5 2 0 4 Updated Feb 24, 2025
  • libblifparse Public

    Parsing library for BLIF netlists

    C++ 18 MIT 10 2 2 Updated Nov 1, 2024
  • tatum Public

    Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits

    C++ 57 MIT 10 3 1 Updated May 28, 2024
  • ezgl Public
    C++ 8 Apache-2.0 5 0 0 Updated Feb 12, 2024
  • libsdcparse Public
    C++ 11 MIT 6 2 1 Updated Jan 29, 2020
  • vtr-buildbot Public

    Buildbot Infrastructure for VTR

    HTML 5 4 0 0 Updated Dec 12, 2019

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