Update dependency edu.berkeley.cs:chisel3-plugin to v3.6.1

[renovate]

This PR contains the following updates:

Package	Update	Change
edu.berkeley.cs:chisel3-plugin (source)	patch	3.6.0 -> 3.6.1

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Release Notes

chipsalliance/chisel (edu.berkeley.cs:chisel3-plugin)

v3.6.1: Chisel v3.6.1

Compare Source

Features

• Implement read-write memory accessors for SyncReadMem (backport #​3190) (by @​mergify[bot] inhttps://github.com/chipsalliance/chisel/pull/32133)
• Allow DataView of Reset <=> [UInt<1>, AsyncReset] (backport #​3181) (by @​mergify[bot] inhttps://github.com/chipsalliance/chisel/pull/32588)
• Fix color emission to check for interactive terminal (backport #​3334) (by @​mergify[bot] inhttps://github.com/chipsalliance/chisel/pull/33355)
  • Chisel will now detect when it should print warnings, errors, and deprecations in color.
    • Color can be controlled with environment variable CHISEL_USE_COLOR. Set to true to force Chisel to use color and false to disable it.
    • Due to how the JVM works, detection requires interactive stdout, stderr, and stdin. Build tools like SBT virtualize stdin and thus color will be disabled by default when running a Chisel main with SBT. Detection also requires environment variable TERM to be set to something other than dumb.
• Implement a SyncReadMem wrapper with explicit read, write, and read/write ports (backport #​3228) (by @​mergify[bot] inhttps://github.com/chipsalliance/chisel/pull/33611)
  This SyncReadMem wrapper is instantiated using a new object, SRAM.apply, and invokes .write, .read, and .readWrite to generate a desired number of read, write, and read/write ports. This function returns a new Bundle wire containing the control signals for each requested port.
• SRAM API: Add a parameter to initialize the memory (backport #​3364) (by @​mergify[bot] inhttps://github.com/chipsalliance/chisel/pull/33799)
  SRAM.apply and SRAM.masked now take a contents parameter, by default a None, which is a string path to a binary file on the filesystem which the SRAM should be initialized with.
• Support literals and DontCare in DataView targets (backport #​3389) (by @​mergify[bot] inhttps://github.com/chipsalliance/chisel/pull/33900)
• SRAM API: Add multiple-clocked port API (backport #​3383) (by @​mergify[bot] inhttps://github.com/chipsalliance/chisel/pull/34044)
  Add new SRAM APIs that take three Clock sequences as parameters instead of the number of read/write/read-write ports. This will sequentially instantiate a memory port for each clock in the Clock sequence and drive them accordingly.
• Add Instance.suggestName (backport #​2886) (by @​mergify[bot] inhttps://github.com/chipsalliance/chisel/pull/37233)
  Adds suggestName API for hierarchy instances.
• Implement typeName API for stable Module names (backport #​3130) (by @​mergify[bot] inhttps://github.com/chipsalliance/chisel/pull/41455)
  This gives a flexible way to generate a stable name for a Chisel type, which is useful for problems like generating stable names for Modules and Queues

API Deprecation

• Deprecate calling .viewAs on non-hardware (backport #​3395) (by @​mergify[bot] inhttps://github.com/chipsalliance/chisel/pull/33999)
  Also fix a crash that could occur when viewing a non-Data containing non-hardware Data.

Backend Code Generation

• Don't emit nodes when calling .asBool on a Bool (backport #​3637) (by @​mergify[bot] inhttps://github.com/chipsalliance/chisel/pull/36388)
  This results in a slight improvement to emitted FIRRTL quality

Performance

• Optimize BitPat equals, overlap, and cover (backport #​3285) (by @​mergify[bot] inhttps://github.com/chipsalliance/chisel/pull/32877)
• Convert Vec dynamic index with a literal to static index (backport #​3314) (by @​mergify[bot] inhttps://github.com/chipsalliance/chisel/pull/33188)
• Fix issue where reify would do the same lookup twice (backport #​3392) (by @​mergify[bot] inhttps://github.com/chipsalliance/chisel/pull/33966)

Fixes

• Fix Instantiate for Product parameters (backport #​3210) (by @​mergify[bot] inhttps://github.com/chipsalliance/chisel/pull/32177)
• Don't emit implicit clock warnings for SyncReadMem.readWrite when explicit clocks are used (backport #​3313) (by @​mergify[bot] inhttps://github.com/chipsalliance/chisel/pull/33155)
• Report Builder errors even when exception is thrown (backport #​3341) (by @​mergify[bot] inhttps://github.com/chipsalliance/chisel/pull/33422)
  Chisel will to report multiple errors, but this can be cut short by any thrown Exception which would then take precedence over the previously encountered errors. Now Chisel will prioritize reporting errors even if an Exception is thrown.
• Add messages to require statements in Math (backport #​3385) (by @​mergify[bot] inhttps://github.com/chipsalliance/chisel/pull/33877)
  • log2 functions
    • unsignedBitLength
• Sanitize Record._elements (backport #​3419) (by @​mergify[bot] inhttps://github.com/chipsalliance/chisel/pull/34266)
  Fixes a bug in D/I where unsanitary names would lead to a crash. It also makes the Printable output for Bundles and Records use the sanitary names which makes them better match the FIRRTL.
• Fix DataMirror.internal.chiselTypeClone to preserve Scala type (backport #​3553) (by @​mergify[bot] inhttps://github.com/chipsalliance/chisel/pull/35544)
• Fix Decodetable (backport #​3563) (by @​mergify[bot] inhttps://github.com/chipsalliance/chisel/pull/35799)
• Add type ascription to implicits from instantiable (backport #​3615) (by @​mergify[bot] inhttps://github.com/chipsalliance/chisel/pull/36177)
  This fixes Scala compiler warnings in Scala 2.13.12 requiring type ascriptions on public implicit definitions.
• Support === on empty Aggregates (backport #​3747) (by @​mergify[bot] inhttps://github.com/chipsalliance/chisel/pull/37499)
• Fix Reg() to properly handle clocks as rvalues (backport #​3775) (by @​mergify[bot] inhttps://github.com/chipsalliance/chisel/pull/37788)
  • Clocks are now properly supported by DataView (including FlatIO)
  • Users will also received better error messages when providing invalid clocks to Reg()
• Report source locator in when scoping error messages (backport #​3804) (by @​mergify[bot] inhttps://github.com/chipsalliance/chisel/pull/38066)
• Fix === for abstract Reset types (backport #​3979) (by @​mergify[bot] inhttps://github.com/chipsalliance/chisel/pull/39800)
  Previously, the function would infinitely recurse resulting in a stack overflow.
• Fix widths for literal values in Bundle literals (backport #​4082) (by @​mergify[bot] inhttps://github.com/chipsalliance/chisel/pull/40900)
  Previously, the user-specified (or unspecified minimum width) of the literal would be used in some operations like concatenation. For literal values that are too-wide, they will now truncate to the correct width. This will become a warning (then later an error) in newer major versions of Chisel.

Documentation

• [fix] typo fix: chosen port of arbiter is not onehot but UInt (backport #​3235) (by @​mergify[bot] inhttps://github.com/chipsalliance/chisel/pull/32600)
  Just a oneline fix to the comment of Arbiter chosen port
• Changed Array to Seq in MuxLookup explantation (backport #​3547) (by @​mergify[bot] inhttps://github.com/chipsalliance/chisel/pull/35499)
• Update CONTRIBUTING.md (backport #​3785) (by @​mergify[bot] inhttps://github.com/chipsalliance/chisel/pull/37866)
  Update CONTRIBUTING instructions to clarify backport process and branch to target.
• [website] Update chisel-template repo link to chipsalliance (backport #​3871) (by @​mergify[bot] inhttps://github.com/chipsalliance/chisel/pull/38944)
• Rename Scala CLI template to example (backport #​3917) (by @​mergify[bot] inhttps://github.com/chipsalliance/chisel/pull/39188)
  Existing links to https://github.com/chipsalliance/chisel/releases/latest/download/chisel-template.scala should instead use https://github.com/chipsalliance/chisel/releases/latest/download/chisel-example.scala
• Add a test for issue 4159 (backport #​4161) (by @​mergify[bot] inhttps://github.com/chipsalliance/chisel/pull/41644)

Dependency Updates

• Add Scala 2.13.11 and 2.12.18 to plugin cross versions (backport #​3327) (by @​mergify[bot] inhttps://github.com/chipsalliance/chisel/pull/33299)
• Add support for Scala 2.13.12 to the compiler plugin (backport #​3527) (by @​mergify[bot] inhttps://github.com/chipsalliance/chisel/pull/35299)
• Add Scala 2.13.13 to cross-build (backport #​3851) (by @​mergify[bot] inhttps://github.com/chipsalliance/chisel/pull/38622)
• Add Scala 2.13.14 to cross-build (backport #​4044) (by @​mergify[bot] inhttps://github.com/chipsalliance/chisel/pull/40455)

Build and Internal Changes

• Read previousVersions for bincompat checking from a file (backport #​3202) (by @​mergify[bot] inhttps://github.com/chipsalliance/chisel/pull/32077)
• Add workflow to automatically update binary compatibility checks (backport #​3242) (by @​mergify[bot] inhttps://github.com/chipsalliance/chisel/pull/32499)
• Add new workflow to fixup backports for release notes (backport #​3252) (by @​mergify[bot] inhttps://github.com/chipsalliance/chisel/pull/32533)
  Improve backport automation so that release notes generation from backport PRs works properly.
• SemanticDB requires private fields of case class to use "val" (backport #​3270) (by @​mergify[bot] inhttps://github.com/chipsalliance/chisel/pull/32711)
• Fix BuildInfo in 3.6.x (by @​sequencer in https://github.com/chipsalliance/chisel/pull/3371)
• Update Scala CLI Template (backport #​3757) (by @​mergify[bot] inhttps://github.com/chipsalliance/chisel/pull/37588)
  • Use "dep" instead of deprecated "lib"
  • Move ChiselStage import above import chisel3._
    • This makes users less likely to run into issues adding import chisel3.util._
  • Bump versions in Github workflows
• Enhance release notes automation (backport #​3751) (by @​mergify[bot] inhttps://github.com/chipsalliance/chisel/pull/37766)
  • Bump mikepenz/release-changelog-builder-action to v4.1.1
  • It now tabs every line included in the Release Notes section of the PR template
• [ci] Stop copying body over to backports in backport-fixup (backport #​4005) (by @​mergify[bot] inhttps://github.com/chipsalliance/chisel/pull/40488)
• [3.6.x] Modernize Release Flow (by @​jackkoenig in https://github.com/chipsalliance/chisel/pull/4213)

Full Changelog: chipsalliance/chisel@v3.6.0...v3.6.1

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