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Fixing the tlfront with clock source node
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@vikramjain236
vikramjain236 committed May 2, 2024
1 parent 82c5aaa commit d782c34
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Showing 3 changed files with 125 additions and 98 deletions.
108 changes: 54 additions & 54 deletions src/main/scala/tilelink/UCITLFront.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -23,7 +23,7 @@ import sideband._
*/
class UCITLFront(val tlParams: TileLinkParams, val protoParams: ProtocolLayerParams,
val fdiParams: FdiParams)
(implicit p: Parameters) extends LazyModule {
(implicit p: Parameters) extends ClockSinkDomain(ClockSinkParameters())(p) {

val device = new SimpleDevice("ucie-front", Seq("ucie,ucie0"))

Expand All @@ -49,40 +49,40 @@ class UCITLFront(val tlParams: TileLinkParams, val protoParams: ProtocolLayerPar
val clientNode: TLClientNode = TLClientNode(Seq(TLMasterPortParameters.v1(
Seq(TLMasterParameters.v1(
name = "ucie-client",
sourceId = IdRange(0, 32),
sourceId = IdRange(0, 1 << tlParams.sourceIDWidth),
requestFifo = true,
visibility = Seq(AddressSet(tlParams.ADDRESS, tlParams.ADDR_RANGE))
)))))

lazy val module = new UCITLFrontImp(this)
}
override lazy val module = new UCITLFrontImp

class UCITLFrontImp(outer: UCITLFront) extends LazyModuleImp(outer) {
class UCITLFrontImp extends Impl {
val io = IO(new Bundle {
// val sbus_clk = Input(Clock()) // System bus clock
// val sbus_reset = Input(Bool()) // System bus reset
// val lclk = Input(Clock()) // lclk is the FDI signalling clock
// val lreset = Input(Bool()) // should the UCIe modules have its own reset?
val fdi = new Fdi(outer.fdiParams)
val fdi = new Fdi(fdiParams)
})
withClockAndReset(clock, reset) {

val fault = RegInit(false.B) // if fault in ecc code

// Instantiate the agnostic protocol layer
val protocol = Module(new ProtocolLayer(outer.fdiParams))
val protocol = Module(new ProtocolLayer(fdiParams))
io.fdi <> protocol.io.fdi
protocol.io.fault := fault

// Hamming encode and decode
val hammingEncoder = Module(new HammingEncode(outer.protoParams))
val hammingDecoder = Module(new HammingDecode(outer.protoParams))
val hammingEncoder = Module(new HammingEncode(protoParams))
val hammingDecoder = Module(new HammingDecode(protoParams))
// Defaults
hammingEncoder.io.data := 0.U
hammingDecoder.io.data := 0.U
hammingDecoder.io.checksum := 0.U

//Sideband node for protocol layer
val protocol_sb_node = Module(new SidebandNode((new SidebandParams), outer.fdiParams))
val protocol_sb_node = Module(new SidebandNode((new SidebandParams), fdiParams))

protocol_sb_node.io.outer.rx.bits := protocol.io.fdi.lpConfig.bits
protocol_sb_node.io.outer.rx.valid := protocol.io.fdi.lpConfig.valid
Expand All @@ -92,33 +92,33 @@ class UCITLFrontImp(outer: UCITLFront) extends LazyModuleImp(outer) {
protocol.io.fdi.plConfig.valid := protocol_sb_node.io.outer.tx.valid
protocol_sb_node.io.outer.tx.credit := protocol.io.fdi.plConfigCredit

protocol_sb_node.io.inner.layer_to_node.bits := Cat(outer.regNode.module.io.sb_csrs.sideband_mailbox_sw_to_node_data_high,
outer.regNode.module.io.sb_csrs.sideband_mailbox_sw_to_node_data_low,
outer.regNode.module.io.sb_csrs.sidebank_mailbox_sw_to_node_index_high,
outer.regNode.module.io.sb_csrs.sideband_mailbox_sw_to_node_index_low)
protocol_sb_node.io.inner.layer_to_node.valid := outer.regNode.module.io.sb_csrs.sideband_mailbox_sw_valid
protocol_sb_node.io.inner.layer_to_node.bits := Cat(regNode.module.io.sb_csrs.sideband_mailbox_sw_to_node_data_high,
regNode.module.io.sb_csrs.sideband_mailbox_sw_to_node_data_low,
regNode.module.io.sb_csrs.sidebank_mailbox_sw_to_node_index_high,
regNode.module.io.sb_csrs.sideband_mailbox_sw_to_node_index_low)
protocol_sb_node.io.inner.layer_to_node.valid := regNode.module.io.sb_csrs.sideband_mailbox_sw_valid

outer.regNode.module.io.sb_csrs.sideband_mailbox_index_low := protocol_sb_node.io.inner.node_to_layer.bits(31, 0)
outer.regNode.module.io.sb_csrs.sideband_mailbox_index_high := protocol_sb_node.io.inner.node_to_layer.bits(63, 32)
outer.regNode.module.io.sb_csrs.sideband_mailbox_data_low := protocol_sb_node.io.inner.node_to_layer.bits(95, 64)
outer.regNode.module.io.sb_csrs.sideband_mailbox_data_high := protocol_sb_node.io.inner.node_to_layer.bits(127, 96)
protocol_sb_node.io.inner.node_to_layer.ready := outer.regNode.module.io.sb_csrs.sideband_mailbox_ready
outer.regNode.module.io.sb_csrs.sideband_mailbox_valid := protocol_sb_node.io.inner.node_to_layer.valid

val tlBundleParams = new TLBundleParameters(addressBits = outer.tlParams.addressWidth,
dataBits = outer.tlParams.dataWidth,
sourceBits = outer.tlParams.sourceIDWidth,
sinkBits = outer.tlParams.sinkIDWidth,
sizeBits = outer.tlParams.sizeWidth,
regNode.module.io.sb_csrs.sideband_mailbox_index_low := protocol_sb_node.io.inner.node_to_layer.bits(31, 0)
regNode.module.io.sb_csrs.sideband_mailbox_index_high := protocol_sb_node.io.inner.node_to_layer.bits(63, 32)
regNode.module.io.sb_csrs.sideband_mailbox_data_low := protocol_sb_node.io.inner.node_to_layer.bits(95, 64)
regNode.module.io.sb_csrs.sideband_mailbox_data_high := protocol_sb_node.io.inner.node_to_layer.bits(127, 96)
protocol_sb_node.io.inner.node_to_layer.ready := regNode.module.io.sb_csrs.sideband_mailbox_ready
regNode.module.io.sb_csrs.sideband_mailbox_valid := protocol_sb_node.io.inner.node_to_layer.valid

val tlBundleParams = new TLBundleParameters(addressBits = tlParams.addressWidth,
dataBits = tlParams.dataWidth,
sourceBits = tlParams.sourceIDWidth,
sinkBits = tlParams.sinkIDWidth,
sizeBits = tlParams.sizeWidth,
echoFields = Nil,
requestFields = Nil,
responseFields = Nil,
hasBCE = false)

val client_tl = outer.clientNode.out(0)._1
val client_edge = outer.clientNode.out(0)._2
val manager_tl = outer.managerNode.in(0)._1
val manager_edge = outer.managerNode.in(0)._2
val client_tl = clientNode.out(0)._1
val client_edge = clientNode.out(0)._2
val manager_tl = managerNode.in(0)._1
val manager_edge = managerNode.in(0)._2

val clientParams = client_edge.bundle
val managerParams = manager_edge.bundle
Expand All @@ -139,21 +139,21 @@ class UCITLFrontImp(outer: UCITLFront) extends LazyModuleImp(outer) {
// The TX packets can be A request from manager node or D response from
// the client node. This needs to be arbitrated to be sent to partner die.
// =======================
val txArbiter = Module(new Arbiter(new TLBundleAUnionD(outer.tlParams), 2))
val txATLPayload = Wire(new TLBundleAUnionD(outer.tlParams))
val txDTLPayload = Wire(new TLBundleAUnionD(outer.tlParams))
//val txTLPayload = Wire(new TLBundleAUnionD(outer.tlParams))
val txArbiter = Module(new Arbiter(new TLBundleAUnionD(tlParams), 2))
val txATLPayload = Wire(new TLBundleAUnionD(tlParams))
val txDTLPayload = Wire(new TLBundleAUnionD(tlParams))
//val txTLPayload = Wire(new TLBundleAUnionD(tlParams))

val aHasData = manager_edge.hasData(manager_tl.a.bits)
val rx_fire = protocol.io.TLplData_valid
val uciRxPayload = Wire(new UCIRawPayloadFormat(outer.tlParams, outer.protoParams)) // User-defined UCIe flit for streaming
val uciTxPayload = Wire(new UCIRawPayloadFormat(outer.tlParams, outer.protoParams)) // User-defined UCIe flit for streaming
val uciRxPayload = Wire(new UCIRawPayloadFormat(tlParams, protoParams)) // User-defined UCIe flit for streaming
val uciTxPayload = Wire(new UCIRawPayloadFormat(tlParams, protoParams)) // User-defined UCIe flit for streaming

// defaults
uciRxPayload := 0.U.asTypeOf(new UCIRawPayloadFormat(outer.tlParams, outer.protoParams))
uciTxPayload := 0.U.asTypeOf(new UCIRawPayloadFormat(outer.tlParams, outer.protoParams))
txATLPayload := 0.U.asTypeOf(new TLBundleAUnionD(outer.tlParams))
txDTLPayload := 0.U.asTypeOf(new TLBundleAUnionD(outer.tlParams))
uciRxPayload := 0.U.asTypeOf(new UCIRawPayloadFormat(tlParams, protoParams))
uciTxPayload := 0.U.asTypeOf(new UCIRawPayloadFormat(tlParams, protoParams))
txATLPayload := 0.U.asTypeOf(new TLBundleAUnionD(tlParams))
txDTLPayload := 0.U.asTypeOf(new TLBundleAUnionD(tlParams))

/*
manager_tl.a.ready = (inward.io.enq.ready & ~protocol.io.fdi.lpStallAck &
Expand Down Expand Up @@ -191,7 +191,7 @@ class UCITLFrontImp(outer: UCITLFront) extends LazyModuleImp(outer) {
// Arbitrate the A and D channels from the credited msgs
creditedMsgA.io.out.ready := txArbiter.io.in(0).ready
txArbiter.io.in(0).valid := creditedMsgA.io.out.fire
//txArbiter.io.in(0).bits <> creditedMsgA.io.out.bits.asTypeOf(new TLBundleAUnionD(outer.tlParams))
//txArbiter.io.in(0).bits <> creditedMsgA.io.out.bits.asTypeOf(new TLBundleAUnionD(tlParams))
txArbiter.io.in(0).bits.opcode := creditedMsgA.io.out.bits.opcode
txArbiter.io.in(0).bits.param := creditedMsgA.io.out.bits.param
txArbiter.io.in(0).bits.size := creditedMsgA.io.out.bits.size
Expand All @@ -204,7 +204,7 @@ class UCITLFrontImp(outer: UCITLFront) extends LazyModuleImp(outer) {

creditedMsgD.io.out.ready := txArbiter.io.in(1).ready
txArbiter.io.in(1).valid := creditedMsgD.io.out.fire
//txArbiter.io.in(1).bits <> creditedMsgD.io.out.bits.asTypeOf(new TLBundleAUnionD(outer.tlParams))
//txArbiter.io.in(1).bits <> creditedMsgD.io.out.bits.asTypeOf(new TLBundleAUnionD(tlParams))
txArbiter.io.in(1).bits.opcode := creditedMsgD.io.out.bits.opcode
txArbiter.io.in(1).bits.param := creditedMsgD.io.out.bits.param
txArbiter.io.in(1).bits.size := creditedMsgD.io.out.bits.size
Expand Down Expand Up @@ -233,7 +233,7 @@ class UCITLFrontImp(outer: UCITLFront) extends LazyModuleImp(outer) {
val checksum_reg = RegInit(0.U(64.W))
checksum_reg := hammingEncoder.io.checksum

val tx_pipe = Module(new Pipe(new UCIRawPayloadFormat(outer.tlParams, outer.protoParams), 1))
val tx_pipe = Module(new Pipe(new UCIRawPayloadFormat(tlParams, protoParams), 1))
tx_pipe.io.enq.bits := uciTxPayload
tx_pipe.io.enq.valid := txArbiter.io.out.fire
// Dequeue the TX TL packets and translate to UCIe flit
Expand All @@ -252,8 +252,8 @@ class UCITLFrontImp(outer: UCITLFront) extends LazyModuleImp(outer) {
outwardA.io.credit.ready := tx_pipe.io.deq.valid && creditA
outwardD.io.credit.ready := tx_pipe.io.deq.valid && creditD

val txACredit = WireDefault(0.U(outer.protoParams.creditWidth.W))
val txDCredit = WireDefault(0.U(outer.protoParams.creditWidth.W))
val txACredit = WireDefault(0.U(protoParams.creditWidth.W))
val txDCredit = WireDefault(0.U(protoParams.creditWidth.W))

when(outwardA.io.credit.valid){
txACredit := outwardA.io.credit.bits
Expand Down Expand Up @@ -300,19 +300,19 @@ class UCITLFrontImp(outer: UCITLFront) extends LazyModuleImp(outer) {
// =======================
// TL RX packets coming from the UCIe stack to the System, push on the outward queue
// =======================
val rxTLPayload = Wire(new TLBundleAUnionD(outer.tlParams))
rxTLPayload := 0.U.asTypeOf(new TLBundleAUnionD(outer.tlParams))
val rxTLPayload = Wire(new TLBundleAUnionD(tlParams))
rxTLPayload := 0.U.asTypeOf(new TLBundleAUnionD(tlParams))
// protocol.io.fdi.lpData.irdy := outward.io.enq.ready

// map the uciRxPayload and the plData based on the uciPayload formatting
// map the uciRxPayload to the rxTLPayload TLBundle
when(rx_fire) {
// ucie cmd
uciRxPayload.cmd := protocol.io.TLplData_bits(511, 448).asTypeOf(new UCICmdFormat(outer.protoParams))
uciRxPayload.cmd := protocol.io.TLplData_bits(511, 448).asTypeOf(new UCICmdFormat(protoParams))
// ucie header 1
uciRxPayload.header1 := protocol.io.TLplData_bits(447,384).asTypeOf(new UCIHeader1Format(outer.tlParams))
uciRxPayload.header1 := protocol.io.TLplData_bits(447,384).asTypeOf(new UCIHeader1Format(tlParams))
// ucie header 2
uciRxPayload.header2 := protocol.io.TLplData_bits(383, 320).asTypeOf(new UCIHeader2Format(outer.tlParams))
uciRxPayload.header2 := protocol.io.TLplData_bits(383, 320).asTypeOf(new UCIHeader2Format(tlParams))
// ucie data payload
uciRxPayload.data(3) := protocol.io.TLplData_bits(319,256)
uciRxPayload.data(2) := protocol.io.TLplData_bits(255,192)
Expand Down Expand Up @@ -372,6 +372,6 @@ class UCITLFrontImp(outer: UCITLFront) extends LazyModuleImp(outer) {

// soft resets: can be reset or flush and reset, in flush and reset, the packets are
// sent out before triggering reset
protocol.io.soft_reset := (outer.regNode.module.io.d2d_csrs.d2d_state_can_reset |
outer.regNode.module.io.d2d_csrs.d2d_flush_and_reset)
}
protocol.io.soft_reset := (regNode.module.io.d2d_csrs.d2d_state_can_reset |
regNode.module.io.d2d_csrs.d2d_flush_and_reset)
}}}
28 changes: 24 additions & 4 deletions src/test/scala/protocol/FdiLoopbackTest.scala
View file
Original file line number Diff line number Diff line change
Expand Up @@ -7,6 +7,7 @@ import chiseltest._
import org.chipsalliance.cde.config.{Field, Parameters, Config}
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
import freechips.rocketchip.prci._
import freechips.rocketchip.diplomacy._
// import freechips.rocketchip.unittest._
import edu.berkeley.cs.ucie.digital.interfaces.FdiParams
Expand All @@ -21,6 +22,9 @@ class FdiLoopbackTester (implicit p: Parameters) extends LazyModule {
val delay = 0.0
val txns = 10

// Create clock source
val clockSourceNode = ClockSourceNode(Seq(ClockSourceParameters()))

val csrfuzz = LazyModule(new TLFuzzer(txns))
val fuzz = LazyModule(new TLFuzzer(txns))
val tlUcieDie1 = LazyModule(new UCITLFront(tlParams=tlParams,
Expand All @@ -29,20 +33,23 @@ class FdiLoopbackTester (implicit p: Parameters) extends LazyModule {
// val fdiLoopback = LazyModule(new FdiLoopback(fdiParams))
// val tlUcieDie2 = LazyModule()

tlUcieDie1.clockNode := clockSourceNode
// CSR node
tlUcieDie1.regNode.node := csrfuzz.node
// connect data nodes
tlUcieDie1.managerNode := fuzz.node
tlUcieDie1.managerNode := TLSourceShrinker(tlParams.sourceIDWidth) := fuzz.node
ram.node := tlUcieDie1.clientNode
// fdiLoopback.ram.node := tlUcieDie1.clientNode
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
val io = IO(new Bundle {
val uci_clock = Input(new ClockBundle(ClockBundleParameters()))
val finished = Output(Bool())
})
// connect IOs
io.finished := fuzz.module.io.finished
val fdiLoopback = Module(new FdiLoopback(fdiParams))
io.uci_clock <> clockSourceNode.out(0)._1
// inputs to tlUcieDie1
tlUcieDie1.module.io.fdi.lpData.ready := fdiLoopback.io.fdi1.lpData.ready
tlUcieDie1.module.io.fdi.plData := fdiLoopback.io.fdi1.plData
Expand Down Expand Up @@ -93,18 +100,31 @@ class FdiLoopbackTester (implicit p: Parameters) extends LazyModule {
tlUcieDie1.module.io.fdi.lpConfigCredit := fdiLoopback.io.fdi1.lpConfigCredit
}
}

class FDITLTestHarness(implicit val p: Parameters) extends Module with HasSuccessIO {
val tester = Module(LazyModule(new FdiLoopbackTester).module)
tester.io.uci_clock.clock := clock
tester.io.uci_clock.reset := reset
io.success := tester.io.finished

// Dummy plusarg to avoid breaking verilator builds with emulator.cc
val useless_plusarg = PlusArg("useless_plusarg", width=1)
dontTouch(useless_plusarg)
ElaborationArtefacts.add("plusArgs", PlusArgArtefacts.serialize_cHeader)
}

class FdiLoopbackTest extends AnyFlatSpec with ChiselScalatestTester {
behavior of "FdiLoopback"
val txns = 2
val timeout = 1000
implicit val p: Parameters = Parameters.empty
it should "finish request and response before timeout" in {
test(LazyModule(new FdiLoopbackTester()).module) {c => //.withAnnotations(Seq(VcsBackendAnnotation, WriteVcdAnnotation))
test(new FDITLTestHarness()).withAnnotations(Seq(VcsBackendAnnotation, WriteVcdAnnotation)) {c => //.withAnnotations(Seq(VcsBackendAnnotation, WriteVcdAnnotation))
println("start Fdi Loopback Test")
c.clock.setTimeout(timeout+10)
c.clock.step(timeout)
c.io.finished.expect(true.B)
println("Fdi Loopback Test finished? " + c.io.finished.peek())
c.io.success.expect(true.B)
println("Fdi Loopback Test finished? " + c.io.success.peek())
}
}
}
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