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+<!DOCTYPE html>
+<html>
+<head>
+  <meta charset="UTF-8">
+  <title>UC Berkeley EE 194/290C</title>
+  <meta name="viewport" content="width=device-width, initial-scale=1.0">
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+    $(document).ready(function() {
+      $(".navbar.ui.dropdown").dropdown({
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+      $("table").addClass("ui celled table");
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+    img {
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+<body>
+  <div class="ui large top fixed menu">
+    <div class="ui container">
+      <a class="header item" href="/">
+        EE 194/290C Tapeout/Bringup
+      </a>
+      <div class="ui navbar dropdown link item">
+        Semesters
+        <div class="menu">
+          <a class="item" href="https://ucb-ee290c.github.io/semesters/fa21">Fa21 Bringup</a>
+          <a class="item" href="https://ucb-ee290c.github.io/semesters/sp22">Sp22 Tapeout</a>
+          <a class="item" href="https://ucb-ee290c.github.io/semesters/fa22">Fa22 Bringup</a>
+          <a class="item" href="https://bwrcrepo.eecs.berkeley.edu/ee290c_ee194_intech22/sp23-course-website">Sp23 Tapeout (Access Required)</a>
+          <a class="item" href="https://ucb-ee290c.github.io/semesters/fa23">Fa23 Bringup</a>
+        </div>
+      </div>
+      <div class="ui navbar dropdown link item">
+        Bringup Tools
+        <div class="menu">
+          <a class="item" href="https://ucb-ee290c.github.io/tools/chip-adapters">Chip Adapters</a>
+        </div>
+      </div>
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+        Help
+        <div class="menu">
+          <a class="item" href="https://ucb-ee290c.github.io/help/acronyms">Acronyms</a>
+          <a class="item" href="https://ucb-ee290c.github.io/help/conventions">Conventions</a>
+        </div>
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+    </div>
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+<!DOCTYPE html>
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+  <meta http-equiv="refresh" content="0; url='https://ucb-ee290c.github.io/semesters/fa23/'"/>
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diff --git a/semesters/fa21/index.md b/semesters/fa21/index.md
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+---
+layout: default
+title: Fa21 Bringup
+container_type: text
+---
+
+## Bringup of OsciBear Chip
+
+In the Spring 2021 Tapeout class, approximately 20 students worked  to design a mixed signal radio mote chip, OsciBear, in the TSMC 28nm process.  The spec is found here:
+
+[Osci Bear SoC Spec](https://docs.google.com/document/d/10uwl_-CENBxfJ_ImlIpCOv1I7NRhQ8Hcbgg7V-u7BpE/edit?usp=sharing)
+
+The bringup effort was not an official class yet, (the first official Bringup class wasn't until Fall 2022) but a number of students worked on  bringup anyway.  It involved:
+
+#### Analog
+
+- verifying the chip drew the expected amount of current (Iddq) and there were no shorts 
+- verifying the LDOs were operable
+
+#### Digital
+- TSI
+  - TSI clock was outputted from the chip
+  - TSI ready/valid signals and all input/output polarities were correct
+  - currently just need to configure TSI module on VCU118 to completely match the one on OsciBear
+- JTAG
+  - testing with a JTAG connector failed, we were unable to figure out why
+  - the JTAG state machine returned correct values, so we narrowed the problem down to the debug transfer module (DTM), which sits between the CPU core and the JTAG state machine
+- SPI
+  - dead due to issues described below
+#### Issues
+  - problems with custom verilog wrapper:
+    - some of the signals were named incorrectly, this led to these signals being tied low
+      - SPI: inoperable
+      - JTAG: only the output enable signal was tied low, which in theory should yield correct behavior because the IO cells are active low (i.e. the jtag out IO cell is always enabled, so jtag data out is always seen on this pin)
+  - FMC connector
+    - the first revision of the PCB did not had through-hole (is that what they're called?) vias instead of filled vias, so the FMC connector couldn't be connected
+      - as a result, we couldn't verify the FMC connections until rev 2
+    - the second revision has an FMC connector, BUT we accidentally connected the chip to pins on the FMC connector that are unconnected on the FPGA
+      - our incorrect assumption here was that the VCU118 supported all of the FMC pins (see pg 97-98 of the VCU118 Evaluation Board User Guide (UG1224) for the pins that are actually supported)
+      - through bad luck we just happened to map to the wrong pins (following a template for another PCB that used the FMCP connector on the VCU118 board)
+      - the VCU118 actually has FMC and FMCP connectors (FMCP just has more pins), and the FMC connector can connect to the FMCP connector...
+        - BUT we can't plug the test PCB FMC to the VCU118 FMCP because there are other PCB components on the VCU118 that stick out too much and prevent them from being connected (the VCU118 is a $10k board so we definitely can't de-solder those components...)
+
+Below is a compilation of useful links throughout the testing process.
+
+## Useful Links
+
+Digital bringup tutorial + log: [Digital Bringup Flow](https://docs.google.com/document/d/1tNKUDFWHfy4b8DfXr9KtJun77Pim8H7qfVuZCEdhlm4/edit?usp=sharing)
+
+Bringup google drive folder: [Bringup](https://drive.google.com/drive/folders/1mHImadMlgaEqb85clPUeMMEmCS_kxW4K)
+
+Directions for powering on PCB and jumper positions: [Bringup of First Board TODO](https://docs.google.com/document/d/1tQ3RLD4XybyNW1Y-uKpsSqgMtGZKb2ivfOpA7K6OlVw/edit)
+
+PCB Git repo: https://github.com/ucberkeley-ee290c/OSCI-bear-pcb
+
+PCB Diagram: Oski_Bear_PCB.pdf
+Chipyard fork for bringup repo: https://github.com/ucberkeley-ee290c/chipyard-osci-bringup.git
+
+Chipyard fork for spring 2021 chip: https://github.com/ucberkeley-ee290c/sp21-chipyard-osci
+
+Bringup files repo: https://github.com/ucberkeley-ee290c/osci-bringup
+
+feel free to refactor this repo as you see fit, I kinda just threw it together last minute
+
+FMC pin map: [FMC Map](https://docs.google.com/spreadsheets/d/16-nCCk_3moKHb_6ItA0S6j3e3JswvQEv1zem66fprEg/edit?usp=sharing)
diff --git a/semesters/fa22/hw/hw-1.md b/semesters/fa22/hw/hw-1.md
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+---
+layout: default
+title: Fa22 Bringup
+---
+
+# HW 1
+
+1. Run through the Altium tutorial. 
+
+2. On a PCB, what does the unit “ounces of copper” mean (as in “2 oz copper”, “0.5 oz copper”) ?
+
+3. If I have a wire that is 1mm wide and 100 mm long on a 1 oz copper PCB, 
+
+  - a. How thick is it? 
+  - b. What are the dimensions in mils? 
+  - c. What is the resistance at DC? 
+  - d. Considering skin depth, what is the resistance at 1 MHz, 100 MHz and 2.4 GHz? Should I worry much about these resistances with milliamp currents and/or 50 Ohm termination resistances? 
+
+
+
+4. Look online for information about transmission lines on PCBs. Try to find: 
+
+  - a. The signal wavelength as a function of frequency of signals and type of PCB.
+  - b. support for Bob’s claim that below 100 MHz we don’t have to worry much.
+  - c. Suggestions for what to do with 500 MHz signals (ML clock) 
+  - d. Suggestions for what to do with 2.4 GHz signals (radio on MS chip) 
+
+5. Read spec docs. Try to find the first things that you might test. Regulated voltages, clock frequencies, supply ripple, 3-wire bus, boot signals of any kind, … For each thing that you want to measure, list the equipment that you would need to measure it, e.g. power supply, oscilloscope, function generator, logic analyzer, spectrum analyzer, vector network analyzer. 
diff --git a/semesters/fa22/hw/hw-2.md b/semesters/fa22/hw/hw-2.md
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+---
+layout: default
+title: Fa22 Bringup
+---
+
+# HW 2
+
+## Introduction
+
+First, fill out this form to indicate your experience/interests in this material: https://forms.gle/3gb2CYGB9saSujPz6. **Do this by Monday, September 19 at 9:00am.**
+
+For this assignment, you will be going through lots of documentation and trying to get a sense of where to start in the chip bringup process.
+
+Throughout this assignment, there are **bolded questions** to which you should write some brief responses to and submit on bCourses by **Wednesday, September 21 at 9:00am** (before class).
+
+Things to keep in mind:
+
+- There are LOTS of files involved. This is simply from trying to document all steps of the chip design and testing, so it is inherent to a chip bringup process and can definitely be daunting. Sad to say, more is better than less so that there is no information loss. So it is normal to be overwhelmed!
+
+- You will never feel like you have the whole picture! You are inheriting these chips from another class, and will never have access to all the information they had while designing the chip (even if you were involved in the design of that chip). Become comfortable with abstracting away certain details, but do make a note of information that is missing that we should ask the chip designers.
+
+- On that note, ***add comments to any of the google docs you read through if something is unclear/seems incorrect.*** We need to keep track of what information is missing in order to understand these chips and test them.
+
+## Chip Spec
+
+Read through the [OsciBear Spec](https://docs.google.com/document/d/10uwl_-CENBxfJ_ImlIpCOv1I7NRhQ8Hcbgg7V-u7BpE/edit?usp=sharing). In particular, look at the block diagram in section 2. *Functional Description* and the I/Os in section 2.0. *Chip-Level I/O*. **What kind of pins/information can you see are exposed to the outside world that could be tested immediately?** Think in terms of power delivery, I/O polarity, etc. **What kind of things CANNOT be tested?** (i.e. things that rely on a test PCB, booting the core, etc.). 
+
+## Initial "smoke testing"
+
+Now skim through the first bringup [design review on 12/1/2021](https://docs.google.com/presentation/d/1KymkU8tKulxSDoUpuweISg_AbTvKxfqzv6RSfXOryTY/edit?usp=sharing) that was conducted after ~2 months of having the OsciBear chips back.  All we had initially was the packaged chips (slide 3 shows the bare die with the "ee290c spring 2021" logo we drew onto the chip).  We soldered these packaged chips onto a breakout board we purchased that was made for the QFN48 chip footprint, which allowed us to run some initial "smoke" tests to check for shorts, see slide 4.
+
+For the smoke testing process, look at the [initial Power Up Notes](https://docs.google.com/document/d/1KYSjdGWSFuDZxZvCflh7EnQ_03_1wnP-xUctJqhpxwQ/edit?usp=sharing). **Summarize what the power up steps are doing, referencing the chip block diagram from the OsciBear Spec.** It would help to be familiar with what an LDO (low dropout) regulator is, google it if you are unsure.
+
+## PCB
+
+Look through initial [OsciBear bringup plan](https://docs.google.com/presentation/d/1Gs47-yamfl0baSdKDYVHiiUFpn6sJ_40/edit?usp=sharing&ouid=101719282076225449124&rtpof=true&sd=true) (useful info starts at slide 14). This is the format we were expected to write our bringup plan for the OsciBear chip. **Summarize some of your general comments about the Steps in Testing (slides 22-27).**
+
+A few months after writing this initial test plan, we had a PCB schematic and layout that we shipped out to get manufactured. Look through the [OsciBear PCB Schematic]((https://drive.google.com/file/d/1LTJZ4nYAWx7QoTrBjxlKNDqR4id7Ls6m/view)), and the associated [PCB Test Plan](https://docs.google.com/document/d/1tQ3RLD4XybyNW1Y-uKpsSqgMtGZKb2ivfOpA7K6OlVw/edit?usp=sharing) for testing this PCB. We will redo this test plan on the PCBs in class. **What do the different voltage values at T7, T1, and T2 correspond to in the PCB? What is the purpose of each of these different voltage levels present on the PCB (or give your best guess)?**
diff --git a/semesters/fa22/hw/hw-3.md b/semesters/fa22/hw/hw-3.md
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+---
+layout: default
+title: Fa22 Bringup
+---
+
+# HW 3
+
+## What did you do this semester?
+
+## Where is it documented? 
+
+## What are the next steps? 
diff --git a/semesters/fa22/index.md b/semesters/fa22/index.md
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+---
+layout: default
+title: Fa22 Bringup
+container_type: text
+---
+
+# Bringup Class
+EE194 (Fall 2022): Test Integrated Circuit Chips Designed in Previous Tapeout Classes 
+
+This repo will store any miscellaneous files for the course, as well as links to other useful repos/resources.
+
+## Logistics
+
+We'll be able to use the Cory 119 lab. Four PCs will have the PCB CAD tools loaded. There are also 4 VNAs. 
+
+We will also have the lab bench in Berkeley Wireless Research Center (BWRC) which presently has the test setup for the Spring 2021 OSCI-bear board.
+
+Join Slack Channel.
+
+[EE 194 on Berkeley Course Catalog](https://classes.berkeley.edu/content/2022-fall-eleng-194-002-lec-002)
+
+## Assignments
+
+[HW 1: Getting Started](/semesters/fa22/hw/hw-1)
+
+[HW 2: Reading through documentation & preliminary test plans](/semesters/fa22/hw/hw-2)
+
+[HW 3: Final Reflection ](/semesters/fa22/hw/hw-3)
+
+## Labs
+
+[Lab 1: Chipyard FPGA Bringup Flow](/semesters/fa22/labs/lab1-chipyard/)
+
+[Lab 2: TSI Bootflow](/semesters/fa22/labs/lab2-tsi-flow)
+
+## Course Outline
+
+| Week    | Date       | Content                       |
+| ------- | ---------- | ----------------------------- |
+| Week 1  |            | [EE194 Tapeout/Bringup Drive](https://drive.google.com/drive/u/0/folders/0APCrUcTRXIAQUk9PVA) |
+|         |            | [20220803_Random Thoughts on Chip Testing & Teaching](https://docs.google.com/presentation/d/1EhfamsHIegYxE_1vNWtrOiO1QMp9ypNUxIsxho4KqlU/edit#slide=id.p) |
+|         |            | [20220805_Lessons Learned from Spring 2021 OSCI-Bear Chip Tests](https://docs.google.com/presentation/d/1MHBhotjajM4fdAW4JR_i6oK6v5xzW-pcbVZToH5gvFo/edit#slide=id.g1427656014b_0_3) |
+| Week 2  |            |                              |
+| Week 3  |            |                              |
+| Week 4  |            |                              |
+| Week 5  | 2022-09-21 | [Meeting](https://docs.google.com/document/d/1Km5419CqBslfCA1qe1JWePEmz57WVmdCLcTMwKbBW8U/edit?usp=sharing) |
+| Week 6  | 2022-09-26 | [Apple Design Review I](https://docs.google.com/presentation/d/17_Q4Qk5LK93c_ttrVOz2LPj5H8GzxMcs5nZWHQ0L3yk/edit?usp=sharing) |
+| Week 7  | 2022-10-03 | [Update](https://docs.google.com/presentation/d/129_pJOnf1ApyLQJn8LcqX2ANAH_SKsD1yZ6woONo4lk/edit?usp=sharing) |
+| Week 8  | 2022-10-10 | [Update](https://docs.google.com/presentation/d/1aWP9lF6zp8DtsJMD8lJL9r8q9fXYWEBbAL3H182nBWI/edit?usp=sharing) |
+| Week 9  | 2022-10-19 | [Update](https://docs.google.com/presentation/d/1Xvwcbj76bFKm4Sz8aMEsMAGsis0sWr44AMWnvR6_3-E/edit?usp=sharing) |
+| Week 10 | 2022-10-24 | [Update](https://docs.google.com/presentation/d/1yDfNDvQJVnOCDaEoNHrRo1JOAEkMq46t_REtFlQ_Vwc/edit?usp=sharing) |
+|         | 2022-10-29 | [Update](https://docs.google.com/presentation/d/1yDfNDvQJVnOCDaEoNHrRo1JOAEkMq46t_REtFlQ_Vwc/edit?usp=sharing) |
+|         | 2022-10-31 | [Apple Design Review II](https://docs.google.com/presentation/d/1iDPyIGFz_Xw0eEvvXmaKGS6GCsI4fZcAKgjCLHd5bi8/edit?usp=sharing) |
+| Week 11 | 2022-11-02 | [Update](https://docs.google.com/presentation/d/18P1khDYTvsB9XXwr8YtZd6hpH6u_zZBjb727s-X0WZk/edit?usp=sharing) |
+| Week 12 | 2022-11-07 | [Update](https://docs.google.com/presentation/d/1-Abu5cl15DvHtvYsPTBOpQ5xzWelwRws3n3af5yI3wg/edit?usp=sharing) |
+| Week 13 | 2022-11-14 | [PCB Design Review](https://docs.google.com/presentation/d/161sD6gMQ4hIzosJ8ylL49r-S_ou4vW2nuJGmH2Xytus/edit?usp=sharing) |
+| Week 14 | 2022-11-23 | *Thanksgiving Break* |
+| Week 15 | 2022-11-28 | [End of Semester Review](https://docs.google.com/presentation/d/1Hxk8DV51aN0ktAccGCqB__tiIEt0CGyqLiahisIFJPg/edit?usp=sharing) |
+| Week 16 | 2022-12-07 | [Apple Design Review III](https://docs.google.com/presentation/d/1_ljUnGtYGW1td-KUE2U49n_JIoQvjNPH0ERVj84UeTY/edit?usp=sharing) |
+
+## Chip Testings
+
+[OSCIBEAR Bringup Note](https://docs.google.com/presentation/d/19t7miUax_Of6cd3P3ku0aEF5J9rQySKc6yDeYJx9vWQ/edit?usp=sharing)
+
+[BearlyML Testing Note](https://docs.google.com/presentation/d/11BuBN2AjHtR5hc7lh9h7Z0UspvnxgiJxumvH6YZSuuI/edit?usp=sharing)
+
+[SCuM-V Testing Note](https://docs.google.com/presentation/d/11fnA0iv8COFCooklE86xab1LmZUoq2lM6CnV4j3MJbs/edit?usp=sharing)
+
+## Resources
+
+### EECS 151 Lectures
+
+[EECS 151 Playlist](https://www.youtube.com/playlist?list=PLkFD6_40KJIxrKaukIqIZMrtSRf6hNdPp)
+
+### Other Git Repos
+[OsciBear Chipyard](https://github.com/ucberkeley-ee290c/chipyard-osci-bringup.git)
+
+[BearlyML](https://github.com/ucberkeley-ee290c/sp22-chipyard-bearlyml) - private for now, ask in Slack for access
+
+[SCuM-V22](https://github.com/ucberkeley-ee290c/sp22-chipyard-scum-v) - private for now, ask in Slack for access
+
+[OsciBear PCB](https://github.com/ucberkeley-ee290c/OSCI-bear-pcb)
+
+## Useful Links
+[OsciBear PCB Schematic](https://drive.google.com/file/d/1LTJZ4nYAWx7QoTrBjxlKNDqR4id7Ls6m/view)
+
+## Course Links
+[Slack](https://join.slack.com/t/194bringup/shared_invite/zt-1fwo87bg1-tyiWNVvH2d1lSRYybVpHJQ)
+
+[bCourses](https://bcourses.berkeley.edu/courses/1518323)
+
+## Staff
+
+### Kristofer Pister
+
+### Nayiri Krzysztofowicz
+
diff --git a/semesters/fa22/labs/lab1-chipyard/assets/TSI.png b/semesters/fa22/labs/lab1-chipyard/assets/TSI.png
diff --git a/semesters/fa22/labs/lab1-chipyard/assets/ali-spec-table.png b/semesters/fa22/labs/lab1-chipyard/assets/ali-spec-table.png
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diff --git a/semesters/fa22/labs/lab1-chipyard/assets/chipyard-flow.PNG b/semesters/fa22/labs/lab1-chipyard/assets/chipyard-flow.PNG
diff --git a/semesters/fa22/labs/lab1-chipyard/assets/chipyard_details.pdf b/semesters/fa22/labs/lab1-chipyard/assets/chipyard_details.pdf
diff --git a/semesters/fa22/labs/lab1-chipyard/assets/css/style.scss b/semesters/fa22/labs/lab1-chipyard/assets/css/style.scss
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+---
+---
+
+// Theme Customizations
+// per https://github.com/pages-themes/cayman#stylesheet
+
+// Colors
+$header-heading-color: #fff !default;
+$header-bg-color: yellow;
+$header-bg-color-secondary: blue;
+$section-headings-color: blue;
+
+@import "{{ site.theme }}";
diff --git a/semesters/fa22/labs/lab1-chipyard/assets/demo.pdf b/semesters/fa22/labs/lab1-chipyard/assets/demo.pdf
diff --git a/semesters/fa22/labs/lab1-chipyard/assets/ee290_bringup_guest_lecture.pdf b/semesters/fa22/labs/lab1-chipyard/assets/ee290_bringup_guest_lecture.pdf
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diff --git a/semesters/fa22/labs/lab1-chipyard/assets/review-final.pdf b/semesters/fa22/labs/lab1-chipyard/assets/review-final.pdf
diff --git a/semesters/fa22/labs/lab1-chipyard/assets/review-mid.pdf b/semesters/fa22/labs/lab1-chipyard/assets/review-mid.pdf
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diff --git a/semesters/fa22/labs/lab1-chipyard/assets/spec-table.png b/semesters/fa22/labs/lab1-chipyard/assets/spec-table.png
diff --git a/semesters/fa22/labs/lab1-chipyard/assets/test-setup.png b/semesters/fa22/labs/lab1-chipyard/assets/test-setup.png
diff --git a/semesters/fa22/labs/lab1-chipyard/assets/timing-path.png b/semesters/fa22/labs/lab1-chipyard/assets/timing-path.png