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Sky130 - Convert to Pydantic, support sky130_scl #848
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Commits on Mar 8, 2024
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Commits on Mar 9, 2024
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Commits on Mar 10, 2024
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perliminary (non-fully-functional) support for sky130_cdl.
synthesis runs until genus breaks on trying to do clock gating with no latches- asking cadence folks on how to fix.
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Commits on Mar 11, 2024
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Commits on Apr 4, 2024
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synthesis runs for commercial tutorial flow.
par fails (either in place_tap_cells or in power_straps if you force it past place_tap_cells with a removal hook due to no tapcells)
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Commits on Apr 5, 2024
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hack around various issues related to the cadence pdk (no
pwell/nwell/li1, clk gating cell disabled?)
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Commits on May 6, 2024
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Commits on Jul 8, 2024
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Commits on Aug 27, 2024
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formatting + [TODO test lvs on more designs] add hardcoded power stra…
…ps hook since we don't have tapcells to reference for rails. This is lvs clean for the sky130-commercial-tutorial (but there are no srams? unsure why)
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seperate drc decks to be library specific, set PEGASUS_DRC to make
pegasus work. drc has like 15 random enclousure violations.. not sure why, they don't seem to be systemic?
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