Merge branch '0.5.x' into 0.5-release

ucb-bar · Jan 12, 2023 · cf454b0 · cf454b0
2 parents 0987d9a + 82df8ed
commit cf454b0
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Showing 3 changed files with 35 additions and 4 deletions.
diff --git a/.github/workflows/setup-oss-cad-suite/action.yml b/.github/workflows/setup-oss-cad-suite/action.yml
@@ -0,0 +1,27 @@
+name: Setup OSS CAD Suite
+
+inputs:
+  osscadsuite-version:
+    description: 'version to install'
+    required: true
+
+runs:
+  using: composite
+  steps:
+    - id: cache-oss-cad-suite
+      uses: actions/cache@v3
+      with:
+        path: oss-cad-suite
+        key: oss-cad-suite-${{ runner.os }}-${{ inputs.osscadsuite-version }}
+
+    - shell: bash
+      if: steps.cache-oss-cad-suite.outputs.cache-hit != 'true'
+      run: |
+        VERSION=${{ inputs.osscadsuite-version }}
+        ARTIFACT=oss-cad-suite-linux-x64-$(echo $VERSION | tr -d '-')
+        wget -q -O - https://github.com/YosysHQ/oss-cad-suite-build/releases/download/${VERSION}/${ARTIFACT}.tgz | tar -zx
+
+    # Add the CAD Suite to the PATH
+    - shell: bash
+      run: echo "$(pwd)/oss-cad-suite/bin" >> $GITHUB_PATH
+
diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml
@@ -117,9 +117,9 @@ jobs:
           z3 --version
           cvc4 --version
       - name: Install Tabby OSS Cad Suite (from YosysHQ)
-        uses: YosysHQ/setup-oss-cad-suite@v1
+        uses: ./.github/workflows/setup-oss-cad-suite
         with:
-          osscadsuite-version: '2022-08-18'
+          osscadsuite-version: '2023-01-09'
       - name: Test
         run: sbt "testOnly -- -n Formal -Dformal_engine=${{ matrix.backend }}"
 

diff --git a/src/main/scala/chiseltest/simulator/ipc/VpiVerilogHarnessGenerator.scala b/src/main/scala/chiseltest/simulator/ipc/VpiVerilogHarnessGenerator.scala
@@ -32,7 +32,12 @@ private[chiseltest] object VpiVerilogHarnessGenerator {
       codeBuffer.append(s"  wire[${width - 1}:0] $name;\n")
     }
 
-    codeBuffer.append(s"  always #`CLOCK_PERIOD $clockName = ~$clockName;\n")
+    codeBuffer.append(s"  initial begin\n")
+    codeBuffer.append(s"    #`CLOCK_PERIOD; // Delay first clock edge to avoid race condition with randomization\n")
+    codeBuffer.append(s"    forever begin\n")
+    codeBuffer.append(s"      #`CLOCK_PERIOD $clockName = ~$clockName;\n")
+    codeBuffer.append(s"    end\n")
+    codeBuffer.append(s"  end\n")
     codeBuffer.append(s"  reg [4095:0] $dumpFileVar = 0;\n")
     codeBuffer.append(s"  reg $dumpOnVar = 0;\n") // this is a hack to exclude the first half-cycle from the wave dump
 
@@ -55,7 +60,6 @@ private[chiseltest] object VpiVerilogHarnessGenerator {
       codeBuffer.append("    /*** Enable VPD dump ***/\n")
       codeBuffer.append("    if ($value$plusargs(\"vcdplusfile=%s\", " + dumpFileVar + ")) begin\n")
       codeBuffer.append(s"      $$vcdplusfile($dumpFileVar);\n")
-      codeBuffer.append(s"      $$dumpfile($dumpFileVar);\n")
       codeBuffer.append(s"      $$dumpvars(0, $dutName);\n")
       codeBuffer.append(s"      $$vcdpluson;\n")
       codeBuffer.append("    end\n")