Merge branch '0.3.x' into 0.3-release

build.sbt

@@ -1,4 +1,4 @@
-// See LICENSE for license details.
+// SPDX-License-Identifier: Apache-2.0
 
 def scalacOptionsVersion(scalaVersion: String): Seq[String] = {
   Seq() ++ {
@@ -55,13 +55,13 @@ pomIncludeRepository := { x => false }
 
 pomExtra := (
 <url>http://chisel.eecs.berkeley.edu/</url>
-<licenses>
-  <license>
-    <name>BSD-style</name>
-    <url>http://www.opensource.org/licenses/bsd-license.php</url>
-    <distribution>repo</distribution>
-  </license>
-</licenses>
+  <licenses>
+    <license>
+      <name>apache_v2</name>
+      <url>https://opensource.org/licenses/Apache-2.0</url>
+      <distribution>repo</distribution>
+    </license>
+  </licenses>
 <scm>
   <url>https://github.com/ucb-bar/chisel-testers2.git</url>
   <connection>scm:git:github.com/ucb-bar/chisel-testers2.git</connection>

build.sc

@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: Apache-2.0
+
 import mill._
 import mill.scalalib._
 import mill.scalalib.publish._

src/main/scala/chisel3/tester/TestAdapters.scala

@@ -1,4 +1,4 @@
-// See LICENSE for license details.
+// SPDX-License-Identifier: Apache-2.0
 
 package chisel3.tester
 

src/main/scala/chisel3/tester/package.scala

@@ -1,4 +1,4 @@
-// See LICENSE for license details.
+// SPDX-License-Identifier: Apache-2.0
 
 package chisel3
 

src/main/scala/chiseltest/ChiselScalatestTester.scala

@@ -1,4 +1,4 @@
-// See LICENSE for license details.
+// SPDX-License-Identifier: Apache-2.0
 
 package chiseltest
 

src/main/scala/chiseltest/ChiselUtestTester.scala

@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: Apache-2.0
+
 package chiseltest
 
 import chiseltest.internal._

src/main/scala/chiseltest/DecoupledDriver.scala

@@ -1,4 +1,4 @@
-// See LICENSE for license details.
+// SPDX-License-Identifier: Apache-2.0
 
 package chiseltest
 

src/main/scala/chiseltest/RawTester.scala

@@ -1,4 +1,4 @@
-// See LICENSE for license details.
+// SPDX-License-Identifier: Apache-2.0
 
 package chiseltest
 

src/main/scala/chiseltest/Region.scala

@@ -1,4 +1,4 @@
-// See LICENSE for license details.
+// SPDX-License-Identifier: Apache-2.0
 
 package chiseltest
 

src/main/scala/chiseltest/ValidDriver.scala

@@ -1,4 +1,4 @@
-// See LICENSE for license details.
+// SPDX-License-Identifier: Apache-2.0
 
 package chiseltest
 

src/main/scala/chiseltest/backends/BackendExecutive.scala

@@ -1,4 +1,4 @@
-// See LICENSE for license details.
+// SPDX-License-Identifier: Apache-2.0
 
 package chiseltest.backends
 

src/main/scala/chiseltest/backends/treadle/OptionsAdapter.scala

@@ -1,4 +1,4 @@
-// See LICENSE for license details.
+// SPDX-License-Identifier: Apache-2.0
 
 package chiseltest.backends.treadle
 

src/main/scala/chiseltest/backends/treadle/TreadleBackend.scala

@@ -1,4 +1,4 @@
-// See LICENSE for license details.
+// SPDX-License-Identifier: Apache-2.0
 
 package chiseltest.backends.treadle
 

src/main/scala/chiseltest/backends/treadle/TreadleExecutive.scala

@@ -1,4 +1,4 @@
-// See LICENSE for license details.
+// SPDX-License-Identifier: Apache-2.0
 
 package chiseltest.backends.treadle
 
@@ -8,7 +8,7 @@ import chisel3.experimental.DataMirror
 import chisel3.MultiIOModule
 import chisel3.stage.{ChiselCircuitAnnotation, ChiselStage}
 import firrtl.annotations.ReferenceTarget
-import firrtl.stage.CompilerAnnotation
+import firrtl.stage.RunFirrtlTransformAnnotation
 import firrtl.transforms.{CheckCombLoops, CombinationalPath}
 import treadle.stage.TreadleTesterPhase
 import treadle.{TreadleCircuitStateAnnotation, TreadleFirrtlFormHint, TreadleTesterAnnotation}
@@ -41,10 +41,10 @@ object TreadleExecutive extends BackendExecutive {
     }.toMap
 
     // This generates the firrtl circuit needed by the TreadleTesterPhase
-    annotationSeq = (new ChiselStage).run(annotationSeq ++ Seq(CompilerAnnotation(new LowFirrtlCompiler)))
+    annotationSeq = (new ChiselStage).run(annotationSeq ++ Seq(RunFirrtlTransformAnnotation(new LowFirrtlEmitter)))
 
     // This generates a TreadleTesterAnnotation with a treadle tester instance
-    annotationSeq = (new TreadleTesterPhase).transform(annotationSeq :+ TreadleFirrtlFormHint(LowForm))
+    annotationSeq = (new TreadleTesterPhase).transform(annotationSeq)
 
     val treadleTester = annotationSeq.collectFirst { case TreadleTesterAnnotation(t) => t }.getOrElse(
       throw new Exception(

src/main/scala/chiseltest/defaults.scala

@@ -1,4 +1,4 @@
-// See LICENSE for license details.
+// SPDX-License-Identifier: Apache-2.0
 
 package chiseltest
 

src/main/scala/chiseltest/exceptions.scala

@@ -1,4 +1,4 @@
-// See LICENSE for license details.
+// SPDX-License-Identifier: Apache-2.0
 
 package chiseltest
 

src/main/scala/chiseltest/experimental/Async.scala

@@ -1,4 +1,4 @@
-// See LICENSE for license details.
+// SPDX-License-Identifier: Apache-2.0
 
 package chiseltest.experimental
 

src/main/scala/chiseltest/experimental/ChiselTestShell.scala

@@ -1,18 +1,4 @@
-/*
-Copyright 2020 The Regents of the University of California (Regents)
-
-Licensed under the Apache License, Version 2.0 (the "License");
-you may not use this file except in compliance with the License.
-You may obtain a copy of the License at
-
-    http://www.apache.org/licenses/LICENSE-2.0
-
-Unless required by applicable law or agreed to in writing, software
-distributed under the License is distributed on an "AS IS" BASIS,
-WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-See the License for the specific language governing permissions and
-limitations under the License.
- */
+// SPDX-License-Identifier: Apache-2.0
 
 package chiseltest.experimental
 

src/main/scala/chiseltest/experimental/TestOptionBuilder.scala

@@ -1,4 +1,4 @@
-// See LICENSE for license details.
+// SPDX-License-Identifier: Apache-2.0
 
 package chiseltest.experimental
 

src/main/scala/chiseltest/experimental/UncheckedClockPeek.scala

@@ -1,4 +1,4 @@
-// See LICENSE for license details.
+// SPDX-License-Identifier: Apache-2.0
 
 package chiseltest.experimental
 

src/main/scala/chiseltest/experimental/UncheckedClockPoke.scala

@@ -1,4 +1,4 @@
-// See LICENSE for license details.
+// SPDX-License-Identifier: Apache-2.0
 
 package chiseltest.experimental
 

src/main/scala/chiseltest/experimental/package.scala

@@ -1,4 +1,4 @@
-// See LICENSE for license details.
+// SPDX-License-Identifier: Apache-2.0
 
 package chiseltest
 

src/main/scala/chiseltest/internal/BackendInterface.scala

@@ -1,4 +1,4 @@
-// See LICENSE for license details.
+// SPDX-License-Identifier: Apache-2.0
 
 package chiseltest.internal
 

src/main/scala/chiseltest/internal/TestEnvInterface.scala

@@ -1,4 +1,4 @@
-// See LICENSE for license details.
+// SPDX-License-Identifier: Apache-2.0
 
 package chiseltest.internal
 

src/main/scala/chiseltest/internal/Testers2.scala

@@ -1,4 +1,4 @@
-// See LICENSE for license details.
+// SPDX-License-Identifier: Apache-2.0
 
 package chiseltest.internal
 

src/main/scala/chiseltest/internal/ThreadedBackend.scala

@@ -1,4 +1,4 @@
-// See LICENSE for license details.
+// SPDX-License-Identifier: Apache-2.0
 
 package chiseltest.internal
 

src/main/scala/chiseltest/legacy/backends/vcs/VcsAnnotations.scala

@@ -1,4 +1,4 @@
-// See LICENSE for license details.
+// SPDX-License-Identifier: Apache-2.0
 
 package chiseltest.legacy.backends.vcs
 

src/main/scala/chiseltest/legacy/backends/vcs/VcsBackend.scala

@@ -1,4 +1,4 @@
-// See LICENSE for license details.
+// SPDX-License-Identifier: Apache-2.0
 
 package chiseltest.legacy.backends.vcs
 

src/main/scala/chiseltest/legacy/backends/vcs/VcsExecutive.scala

@@ -8,7 +8,7 @@ import chisel3.stage.{ChiselCircuitAnnotation, ChiselStage}
 import chiseltest.internal.BackendInstance
 import chiseltest.backends.BackendExecutive
 import firrtl.annotations.{DeletedAnnotation, ReferenceTarget}
-import firrtl.stage.CompilerAnnotation
+import firrtl.stage.RunFirrtlTransformAnnotation
 import firrtl.transforms.CombinationalPath
 
 object VcsExecutive extends BackendExecutive {
@@ -38,7 +38,7 @@ object VcsExecutive extends BackendExecutive {
     System.gc()
 
     val targetDir = annotationSeq.collectFirst {
-      case TargetDirAnnotation(t) => t
+      case firrtl.options.TargetDirAnnotation(t) => t
     }.get
     val targetDirFile = new File(targetDir)
 
@@ -63,7 +63,7 @@ object VcsExecutive extends BackendExecutive {
       .run(
         annotationSeq ++ Seq(
           generatorAnnotation,
-          CompilerAnnotation(new VerilogCompiler())
+          RunFirrtlTransformAnnotation(new VerilogEmitter)
         )
       )
       .filterNot(_.isInstanceOf[DeletedAnnotation])

src/main/scala/chiseltest/legacy/backends/verilator/CommandEditor.scala

@@ -1,4 +1,4 @@
-// See LICENSE for license details.
+// SPDX-License-Identifier: Apache-2.0
 
 package chiseltest.legacy.backends.verilator
 

src/main/scala/chiseltest/legacy/backends/verilator/SimApiInterface.scala

@@ -1,4 +1,5 @@
-// See LICENSE for license details.
+// SPDX-License-Identifier: Apache-2.0
+
 package chiseltest.legacy.backends.verilator
 
 import java.io.File

src/main/scala/chiseltest/legacy/backends/verilator/Utils.scala

@@ -1,4 +1,4 @@
-// See LICENSE for license details.
+// SPDX-License-Identifier: Apache-2.0
 
 package chiseltest.legacy.backends.verilator
 
@@ -98,7 +98,7 @@ trait EditableBuildCSimulatorCommand {
     * @return sequence of strings (suitable for passing as arguments to the simulator builder) specifying a flag and the absolute path to the file.
     */
   def blackBoxVerilogList(dir: java.io.File): Seq[String] = {
-    val list_file = new File(dir, firrtl.transforms.BlackBoxSourceHelper.fileListName)
+    val list_file = new File(dir, firrtl.transforms.BlackBoxSourceHelper.defaultFileListName)
     if(list_file.exists()) {
       Seq("-f", list_file.getAbsolutePath)
     } else {

src/main/scala/chiseltest/legacy/backends/verilator/VerilatorAnnotations.scala

@@ -1,4 +1,4 @@
-// See LICENSE for license details.
+// SPDX-License-Identifier: Apache-2.0
 
 package chiseltest.legacy.backends.verilator
 

src/main/scala/chiseltest/legacy/backends/verilator/VerilatorBackend.scala

@@ -1,4 +1,4 @@
-// See LICENSE for license details.
+// SPDX-License-Identifier: Apache-2.0
 
 package chiseltest.legacy.backends.verilator
 

src/main/scala/chiseltest/legacy/backends/verilator/VerilatorExecutive.scala

@@ -8,8 +8,9 @@ import chisel3.{MultiIOModule, assert}
 import chisel3.experimental.DataMirror
 import chisel3.stage.{ChiselCircuitAnnotation, ChiselStage}
 import firrtl.annotations.ReferenceTarget
-import firrtl.stage.CompilerAnnotation
+import firrtl.stage.RunFirrtlTransformAnnotation
 import firrtl.transforms.CombinationalPath
+import firrtl.util.BackendCompilationUtilities
 
 object VerilatorExecutive extends BackendExecutive {
   import firrtl._
@@ -38,7 +39,7 @@ object VerilatorExecutive extends BackendExecutive {
     System.gc()
 
     val targetDir = annotationSeq.collectFirst {
-      case TargetDirAnnotation(t) => t
+      case firrtl.options.TargetDirAnnotation(t) => t
     }.get
     val targetDirFile = new File(targetDir)
 
@@ -58,7 +59,7 @@ object VerilatorExecutive extends BackendExecutive {
     // - TestCommandOverride
     // - CombinationalPath
     val compiledAnnotations = (new ChiselStage).run(
-      elaboratedAnno :+ CompilerAnnotation(new VerilogCompiler())
+      elaboratedAnno :+ RunFirrtlTransformAnnotation(new VerilogEmitter)
     )
 
     val cppHarnessFileName = s"${circuit.name}-harness.cpp"
@@ -94,7 +95,7 @@ object VerilatorExecutive extends BackendExecutive {
       s"verilator command failed on circuit ${circuit.name} in work dir $targetDir"
     )
     assert(
-      chisel3.Driver.cppToExe(circuit.name, targetDirFile).! == 0,
+      BackendCompilationUtilities.cppToExe(circuit.name, targetDirFile).! == 0,
       s"Compilation of verilator generated code failed for circuit ${circuit.name} in work dir $targetDir"
     )
 

src/main/scala/chiseltest/package.scala

@@ -1,4 +1,4 @@
-// See LICENSE for license details.
+// SPDX-License-Identifier: Apache-2.0
 
 import scala.language.implicitConversions
 import chiseltest.internal._

src/test/scala/chiseltest/experimental/tests/NegativeInputValuesTest.scala

@@ -1,18 +1,4 @@
-/*
-Copyright 2020 The Regents of the University of California (Regents)
-
-Licensed under the Apache License, Version 2.0 (the "License");
-you may not use this file except in compliance with the License.
-You may obtain a copy of the License at
-
-    http://www.apache.org/licenses/LICENSE-2.0
-
-Unless required by applicable law or agreed to in writing, software
-distributed under the License is distributed on an "AS IS" BASIS,
-WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-See the License for the specific language governing permissions and
-limitations under the License.
- */
+// SPDX-License-Identifier: Apache-2.0
 
 package chiseltest.experimental.tests
 

src/test/scala/chiseltest/experimental/tests/VcsBasicTests.scala

@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: Apache-2.0
 package chisel3.experimental.tests
 
 import chisel3._

src/test/scala/chiseltest/experimental/tests/VerilatorBasicTests.scala

@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: Apache-2.0
 package chiseltest.experimental.tests
 
 import chisel3._

src/test/scala/chiseltest/experimental/tests/VerilatorClockPokeTest.scala

@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: Apache-2.0
 package chiseltest.experimental.tests
 
 import chisel3._

src/test/scala/chiseltest/tests/AsyncClockTest.scala

@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: Apache-2.0
+
 package chiseltest.tests
 
 import chisel3._

src/test/scala/chiseltest/tests/AsyncResetTest.scala

@@ -1,4 +1,4 @@
-// See LICENSE for license details.
+// SPDX-License-Identifier: Apache-2.0
 
 package chiseltest.tests
 

src/test/scala/chiseltest/tests/AsyncResetUsingBlackBoxTest.scala

@@ -1,4 +1,4 @@
-// See LICENSE for license details.
+// SPDX-License-Identifier: Apache-2.0
 
 package chiseltest.tests
 

src/test/scala/chiseltest/tests/BasicTest.scala

@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: Apache-2.0
+
 package chiseltest.tests
 
 import org.scalatest._