Add DMI Bridge to FireSim

generators/firechip/src/main/scala/BridgeBinders.scala

@@ -86,6 +86,19 @@ class WithTSIBridgeAndHarnessRAMOverSerialTL extends HarnessBinder({
   }
 })
 
+class WithDMIBridge extends HarnessBinder({
+  case (th: FireSim, port: DMIPort, chipId: Int) => {
+    // This assumes that:
+    // If ExtMem for the target is defined, then FASED bridge will be attached
+    // If FASED bridge is attached, loadmem widget is present
+
+    val hasMainMemory = th.chipParameters(th.p(MultiChipIdx))(ExtMem).isDefined
+    val mainMemoryName = Option.when(hasMainMemory)(MainMemoryConsts.globalName(th.p(MultiChipIdx)))
+    val nDMIAddrBits = port.io.dmi.req.bits.addr.getWidth
+    DMIBridge(th.harnessBinderClock, port.io, mainMemoryName, th.harnessBinderReset.asBool, nDMIAddrBits)(th.p)
+  }
+})
+
 class WithNICBridge extends HarnessBinder({
   case (th: FireSim, port: NICPort, chipId: Int) => {
     NICBridge(port.io.clock, port.io.bits)(th.p)
@@ -139,6 +152,7 @@ class WithSuccessBridge extends HarnessBinder({
 // Shorthand to register all of the provided bridges above
 class WithDefaultFireSimBridges extends Config(
   new WithTSIBridgeAndHarnessRAMOverSerialTL ++
+  new WithDMIBridge ++
   new WithNICBridge ++
   new WithUARTBridge ++
   new WithBlockDeviceBridge ++
@@ -152,6 +166,7 @@ class WithDefaultFireSimBridges extends Config(
 // Shorthand to register all of the provided mmio-only bridges above
 class WithDefaultMMIOOnlyFireSimBridges extends Config(
   new WithTSIBridgeAndHarnessRAMOverSerialTL ++
+  new WithDMIBridge ++
   new WithUARTBridge ++
   new WithBlockDeviceBridge ++
   new WithFASEDBridge ++

generators/firechip/src/main/scala/TargetConfigs.scala

@@ -5,19 +5,13 @@ import java.io.File
 import chisel3._
 import chisel3.util.{log2Up}
 import org.chipsalliance.cde.config.{Parameters, Config}
-import freechips.rocketchip.groundtest.TraceGenParams
 import freechips.rocketchip.tile._
 import freechips.rocketchip.tilelink._
-import freechips.rocketchip.rocket.DCacheParams
 import freechips.rocketchip.subsystem._
-import freechips.rocketchip.devices.tilelink.{BootROMLocated, BootROMParams}
-import freechips.rocketchip.devices.debug.{DebugModuleParams, DebugModuleKey}
-import freechips.rocketchip.diplomacy.{LazyModule}
+import freechips.rocketchip.devices.tilelink.{BootROMLocated}
+import freechips.rocketchip.devices.debug.{DebugModuleKey}
 import freechips.rocketchip.prci.{AsynchronousCrossing}
-import testchipip.iceblk.{BlockDeviceKey, BlockDeviceConfig}
-import testchipip.cosim.{TracePortKey, TracePortParams}
-import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
-import scala.math.{min, max}
+import testchipip.cosim.{TracePortKey}
 
 import chipyard.clocking.{ChipyardPRCIControlKey}
 import chipyard.harness.{HarnessClockInstantiatorKey}
@@ -92,10 +86,10 @@ class WithMinimalFireSimDesignTweaks extends Config(
   new WithBootROM ++
   // Required: Existing FAME-1 transform cannot handle black-box clock gates
   new WithoutClockGating ++
+  // Optional: Do not support debug module w. JTAG until FIRRTL stops emitting @(posedge ~clock)
+  new chipyard.config.WithNoDebug ++
   // Required*: Removes thousands of assertions that would be synthesized (* pending PriorityMux bugfix)
-  new WithoutTLMonitors ++
-  // Required: Do not support debug module w. JTAG until FIRRTL stops emitting @(posedge ~clock)
-  new chipyard.config.WithNoDebug
+  new WithoutTLMonitors
 )
 
 // Non-frequency tweaks that are generally applied to all firesim configs
@@ -109,8 +103,8 @@ class WithFireSimDesignTweaks extends Config(
   new testchipip.serdes.WithSerialTLWidth(4) ++
   // Required*: Scale default baud rate with periphery bus frequency
   new chipyard.config.WithUART(
-    baudrate=BigInt(3686400L), 
-    txEntries=256, rxEntries=256) ++        // FireSim requires a larger UART FIFO buffer, 
+    baudrate=BigInt(3686400L),
+    txEntries=256, rxEntries=256) ++        // FireSim requires a larger UART FIFO buffer,
   new chipyard.config.WithNoUART() ++       // so we overwrite the default one
   // Optional: Adds IO to attach tracerV bridges
   new chipyard.config.WithTraceIO ++
@@ -276,6 +270,13 @@ class FireSimSmallSystemConfig extends Config(
   new freechips.rocketchip.subsystem.WithInclusiveCache(nWays = 2, capacityKB = 64) ++
   new chipyard.RocketConfig)
 
+class FireSimDmiRocketConfig extends Config(
+  new chipyard.harness.WithSerialTLTiedOff ++ // (must be at top) tieoff any bridges that connect to serialTL so only DMI port is connected
+  new WithDefaultFireSimBridges ++
+  new WithDefaultMemModel ++
+  new WithFireSimConfigTweaks ++
+  new chipyard.dmiRocketConfig)
+
 //*****************************************************************
 // Boom config, base off chipyard's LargeBoomV3Config
 //*****************************************************************