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Bump riscv-isa-sim for dtm.h additions
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Submodule riscv-isa-sim
updated
11 files
+1 −1 | .github/workflows/continuous-integration.yml | |
+42 −8 | arch_test_target/spike/model_test.h | |
+27 −19 | disasm/disasm.cc | |
+2 −0 | fdt/fdt.mk.in | |
+10 −0 | fesvr/dtm.h | |
+1 −0 | fesvr/elfloader.cc | |
+9 −5 | riscv/debug_module.cc | |
+6 −1 | riscv/decode_macros.h | |
+3 −3 | riscv/insns/cbo_inval.h | |
+14 −5 | riscv/triggers.cc | |
+4 −2 | riscv/triggers.h |